[ibis-macro] Re: IBIS-to-AMS script update
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: <ibis-macro@xxxxxxxxxxxxx>
- Date: Wed, 8 Feb 2006 14:14:11 -0800
Paul,
Thanks. The Verilog version must have "\" on
the "blank" lines, so you did it right.
I will check it out and let you know what I
found.
Arpad
==============================================
-----Original Message-----
From: ibis-macro-bounce@xxxxxxxxxxxxx [mailto:ibis-macro-bounce@xxxxxxxxxxxxx]
On Behalf Of Paul Fernando
Sent: Wednesday, February 08, 2006 1:57 PM
To: ibis-macro@xxxxxxxxxxxxx
Subject: [ibis-macro] Re: IBIS-to-AMS script update
The updated version is attached.
1) Fixed
2) Modified to only one define (verilog)
3) The VHDL file already had blank lines between tables. In Verilog, can I have
empty
lines in between or do I need "\" on these empty lines? This version has "\"s
to be on
the safe side.
The [... reference] and rise/fall waveform order issues are also fixed.
Thanks,
Paul
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