[SI-LIST] Re: source synchronous constraint
- From: "Jack W.C. Lin" <JackWCLin@xxxxxxxxxxxx>
- To: "'zanglinyuan@xxxxxxxxxx'" <zanglinyuan@xxxxxxxxxx>,si-list@xxxxxxxxxxxxx
- Date: Tue, 27 Aug 2002 10:33:46 +0800
Hi:
I think there is no strong constraints for source synchronous architecture.
Because the key point is in timing skew between data and reference
clock/strobe signals. So if the skew between them meet the spec requirement,
I think the bus will operate normally. But you can set noise margin as your
constraint. I mean for some SI concern, longer trace length will cause worse
SI. From your experience, you can put said 300mV as your noise margin, and
run sweep analysis for trace length variation. You can find out the upper
bound of data or reference clock/strobe's length. I hope it is useful!
Jack W.C. Lin
-----Original Message-----
From: zanglinyuan [mailto:zanglinyuan@xxxxxxxxxx]
Sent: Tuesday, August 27, 2002 10:19 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] source synchronous constraint
Hi:
I am designing some source synchronous system,and need to make PCB routing
constraint.
However,the timing parameter for tranceiver and reciever does not match each
other,
for example :
TX:setuptime=1ns,holdtime=1ns
RX:setuptime=2.5ns,holdtime=0.5ns
even so,I don't think the system won't work if we just route the clk/data's
PCB length within
some tolerance,because the datasheet does't give the valid data time which
is very important for
the PCB constraint to be made.
what's the right way to deal with such case? that's how to make the PCB
routing constraint for this case?
Thanks a lot in advance.
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