[SI-LIST] Re: source synchronous constraint

  • From: zanglinyuan <zanglinyuan@xxxxxxxxxx>
  • To: Scott McMorrow <scott@xxxxxxxxxxxxx>
  • Date: Tue, 27 Aug 2002 11:20:24 +0800


Hi. Scott
It is a typical source synchronous system .

as follows:
____                  _____
|       |  strobe     |          |
|       |------------|          |
|TX  |                 |  RX  |
|       | data         |          |
|___ |----------- |_____|

TX----transceiver
RX----recevier 

The TX parameter is the transceiver ouput  data relative to strobe.
The  RX parameter is the receiver input requirement for data relative to strobe.
The strobe's active edge is rising edge.

The key problem is the tranceiver ouput parameter does't match the receiver's 
input requirement ,
how to deal with  PCB'S routing ?

(TX:setuptime=1ns,holdtime=1ns
RX:setuptime=2.5ns,holdtime=0.5ns )


thanks

 
----- Original Message ----- 
From: Scott McMorrow <scott@xxxxxxxxxxxxx>
To: <zanglinyuan@xxxxxxxxxx>
Sent: Tuesday, August 27, 2002 12:23 PM
Subject: Re: [SI-LIST] source synchronous constraint


> Zanglingyuan,
> 
> It is not clear what your Tx parameters are.  Is this a double data rate 
> source synchronous system where the setup and hold times are relative to 
> the Tx strobe/clock?  If so, what edge of the strobe is the active edge. 
>  Are the Rx setup and hold parameters relative to the same strobe/clock 
> edge?
> 
> regards,
> 
> scott
> 
> 
> -- 
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 239-5536
> http://www.teraspeed.com
> 
> 
> zanglinyuan wrote:
> 
> >Hi:
> >I am designing some source synchronous system,and need to make PCB routing 
> >constraint.
> >However,the timing parameter for tranceiver and reciever does not match each 
> >other,
> >for example :
> >TX:setuptime=1ns,holdtime=1ns
> >RX:setuptime=2.5ns,holdtime=0.5ns 
> >
> >even so,I don't think the system won't work if we just route the clk/data's 
> >PCB length within
> >some tolerance,because the datasheet does't give the valid data time which 
> >is very important for
> >the PCB constraint to be made.  
> >
> >what's the right way  to deal with such case? that's how to make the PCB 
> >routing constraint for this case?
> >
> >Thanks a lot in advance.
> >
> >
> >
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