[SI-LIST] source synchronous constraint
- From: zanglinyuan <zanglinyuan@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 27 Aug 2002 10:19:08 +0800
Hi:
I am designing some source synchronous system,and need to make PCB routing
constraint.
However,the timing parameter for tranceiver and reciever does not match each
other,
for example :
TX:setuptime=1ns,holdtime=1ns
RX:setuptime=2.5ns,holdtime=0.5ns
even so,I don't think the system won't work if we just route the clk/data's PCB
length within
some tolerance,because the datasheet does't give the valid data time which is
very important for
the PCB constraint to be made.
what's the right way to deal with such case? that's how to make the PCB
routing constraint for this case?
Thanks a lot in advance.
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