[SI-LIST] Re: si-list@freelists.org
- From: Rui Pimenta <rpimenta@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 19 Apr 2005 15:11:16 +0200
Dear all,
Thanks a lot for all the answers. I must say that I am a bit more confused
now:) which is
good, meaning that I am probably aware of more problems:))
I think that I can conclude/answer from/to all emails:
- by no means I can use the ferrite beads in such big magnetic field. They
will saturate
and my filter will be completely different. If any filter in the end.
Nevertheless
I'll place a zero Ohm in place. At least to validate the design.
- The front-end electronics cannot be placed outside the magnet. We have to
acquire
analog data(mV) and we have to be as close as possible from source. This is
really out of
the question.
- Probably I'll have to play with all frequency ranges and see where I can
find the best
jitter tolerance.
What I would like to ask is: Besides the rules that Xilinx have in their guides
what
should I take into account inorder to minimize the impact of NOT having the
ferrite beads.
- The output of the FPGA will be connected to a optical transceiver (less than
4 in
away). This will connect to other Virtex-II Pro on other boards.
- I have the DVDs from Xilinx and Dr. Howard Johnson (very very good). So I'll
take
into account the track width, lengths, placement.
- Does it make a different which outputs pins I use? Maybe some are more noise
protected
than others?
- Any other suggestions?
Thanks once more,
Rui Pimenta
On Mon, 18 Apr 2005 17:05:45 -0600
"Mark Alexander" <mark.alexander@xxxxxxxxxx> wrote:
> Rui,
>
> We have done only limited tests without the ferrite beads, which
> generally produced mixed results. I've seen a lot of anecdotal cases
> where designers left the beads out for one reason or another and had
> marginal systems. In 9 out of 10 cases, people end up putting them back
> in and the system works. They're not only needed for protection from
> voltage regulator noise, but also to keep induced noise from one MGT
> away from other MGTs.
>
> I'll check with Murata and let you know what I find. I hadn't
> considered saturation -- you might be right about it.
>
> -mark
>
>
> -----Original Message-----
> From: Rui Pimenta [mailto:rpimenta@xxxxxxxxxx]
> Sent: Monday, April 18, 2005 11:27 PM
> To: mark.alexander
> Subject: Re: [SI-LIST] si-list@xxxxxxxxxxxxx
>
> Dear Mark and Tim,
>
> Apart from the force, I am worried that at such magnetic field the
> ferrite will change
> their properties. Probably they will saturate and then the filter will
> become another
> thing.
>
> In terms of frequency I want as fast as possible. I will have optical
> transceivers close
> to the FPGA ~ 6 in.
>
> I did not contact Murata, I'll do it right away. But if you could get
> some information
> from them would be great.
>
> Did you, (Mark/Xilinx), do any tests without these ferrite beads?
>
> Thank you once more,
> Rui Pimenta
>
>
>
> On Apr 2005 08:23:57 -0600
> "Mark Alexander" <mark.alexander@xxxxxxxxxx> wrote:
>
> > Rui,
> >
> > Are you concerned that these Ferrite beads will experience a force
> from
> > the 5T field? I haven't looked into this myself. Have you consulted
> > Murata on the matter? I've got a contact over there I can check with
> if
> > you like.
> >
> > As for the frequencies you're operating at... Tim wasn't quite right
> > with his comment. Lower data rates don't necessarily equate to higher
> > jitter tolerance or power supply noise rejection, as the
> vulnerabilities
> > of the CDR are fairly complex. Our testing suggests that the best
> > jitter tolerance is achieved between 2.5 Gbps and 3.125 Gbps for the
> > Virtex-2 Pro RocketIO transceivers.
> >
> > -mark
> >
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Rui Pimenta
> > Sent: Monday, April 18, 2005 4:55 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] si-list@xxxxxxxxxxxxx
> >
> > Dear all,
> >
> > I am designing a new PCB boards which contains the Virtex-II pro
> > XC2VP50-5FF1152C. I want
> > to use 12 RocketIO Transceivers with speeds above 1Gb/s.
> >
> > These boards will be working in a heavy-ion detector under a magnetic
> > field of ~5 Tesla.
> >
> > ^^^^^^^^
> >
> > As discribed, in Xilinx user guide ug024 page 111, it is recommended
> the
> > use of ferrite
> > beads from Murata for the power filtering on each transceiver power
> pin.
> >
> > Since I have a magnetic field of ~5 Tesla I have some questions:
> >
> > 1- Is there any other way of designing these power filters without
> using
> > ferrite/coils,
> > and similar performance?
> >
> > 2- What are the risks that I will be taken if I don't place the
> ferrite?
> > The RocketIOs
> > will not work?
> >
> > 3- Any suggestions for overcome this issue?
> >
> >
> > I have inquired Xilinx on this matter and I am waiting for their
> answer.
> > What I am afraid
> > is that their answer may include something like: We cannot guarantee
> > anything that goes
> > out of specs. Which doesn't help me.
> >
> > That is why I am contacting the list seeking for suggestions/advises.
> >
> > Thanks in advance,
> > Rui Pimenta
> >
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