[SI-LIST] Re: return path
- From: "Jon Powell" <jonpowell@xxxxxxxxxxxx>
- To: <upender_ug@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sat, 6 Dec 2003 11:37:59 -0800
The answer is that the current will take the path(s) of least impedance. For
almost any interesting frequency of
clock, this will be under the trace, but at near DC it will be more straight
line shortest distance and spread out in the return plane. This is usually
easiest to understand by calculating the frequency dependent impedance which
quickly becomes dominated by loop inductance in a transmission line.
You ask if you can do a T. You haven't provided enough info for an answer.
In particular, you haven't told us what you are worried about. SI, EMC,
Operation, High Frequency?
For solid plane designs these questions can be answered pretty easily by
just about any SI simulator.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of upender a
Sent: Saturday, December 06, 2003 3:07 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] return path
Dear Experts,
I have the following basic doubts.I have a four layer board with stack
S-G-P-S
I placed a clock source at the Right top corner and the and the and the
slave device at the left hand bottom.
If I route a clock trace in "L" shape(Of course orthogonality has been
avoided ).
will the return curren takes the same "L "shape?
, Or will it takes the shortest path along the diagonal of the board?
Again if I route the clock vertically in the top layer(where the reference
is ground)then the jump to bottom layer where the reference is power plane ,
in this case where the return current flows, still it takes the same "L"
shape?
If i need to connect the clock to two destinations , can i go for a T
connection in top and bottom layers.
Can you provide a qualitative reference in any website.
Thanks and Regards
Ananthoju
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