[SI-LIST] Re: return path

  • From: "Benny Yan" <zyan@xxxxxxxxxx>
  • To: <m_p_sen@xxxxxxxxx>
  • Date: Thu, 30 Aug 2007 14:09:54 +0800

It does not sound a good idea with many split, while It depends on the =
speed of your signals.
For asymmetric stripline, the distance proportion to ground and power =
plane should be concerned.

Benny Yan
IO Methodology Inc.


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of sengottuvel m.p.
Sent: Thursday, August 30, 2007 1:16 PM
To: tbiggs@xxxxxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: return path

Hi all,
=20
When we have stripline trace between power and ground plane with many =
split in power and full plane in ground, is it ok the good return path  =
through ground? or asymmetric stripline i.e. trace near ground is =
preferable?
=20
Thanks,
Sengo

----- Original Message ----
From: Tom Biggs <tbiggs@xxxxxxxxxxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Thursday, August 30, 2007 4:31:08 AM
Subject: [SI-LIST] Re: Conductor loss reduction at High Frequency


There are three things mentioned in this thread that caught my interest:

1. trace/trace core versus trace/power core

Assume that you have two layers around a core. I assume that the side of
a trace next to the center of the core is rougher than the side on the
outside of the core.

Given a nonsymmetrical stripline, more of the current is going to travel
on the side of the trace closest to the nearest ground/power plane.=3D20
--------power
--  trace
--  trace
--------power

If the core is between the trace layers, then the side of the trace
closest to the power plane will be smooth. If the core is between
trace/power layers, then this side of the trace is going to be rough.
You would expect lower loss in the trace/trace core case. True?

2. Surface layers
It was mentioned that with microstrip surface layers that your
impendence is not as well controlled, presumably because the surface
layer is a foil layer so its distance to the next plane layer is not
well controlled, since it is determined by the final press of all
layers, and can vary from build to build.

But, if you use surface layers, you can widen your trace by using more
prepreg layers, giving you:
1. Lower loss (at least for short lengths)
2. It is easier to control the trace thickness and height within a
certain # of mils if the trace is thicker and higher, so if the trace is
thick enough it should be easy to control its impendence, even on an
outer layer. E.g. 12 mils +/- 1 mil has a much tighter impendence
control than 3 mils +/- 1 mil.
I'm not sure if this is enough to compensate for the poor height
control.=3D20
And on the downside:
3. More EMI=3D20
4. More crosstalk (for a given spacing of traces).

3. Tarnishing
How does tarnishing affect the signal?=3D20

   -tom

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scott McMorrow
Sent: Wednesday, August 29, 2007 2:11 PM
To: jeff.loyer@xxxxxxxxx
Cc: sridharam@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Conductor loss reduction at High Frequency

Surface roughness is the largest contributor we've measured for
conductor loss.  There are certain low loss materials that are
constructed with high tooth copper for maximum adhesion, which show
enough loss to absolutely negate any benefit that the low loss (low tan
delta) material would have had over materials with twice the dielectric
loss.

Interesting stuff.

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed(r) is the registered service mark of Teraspeed Consulting
Group LLC



Loyer, Jeff wrote:
> My 2 cents available in the article below:
>
> http://pcdandm.com/cms/content/view/2572/95/
>
>
> Jeff Loyer
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=3D20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of M Sridhar
> Sent: Wednesday, August 29, 2007 5:08 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Conductor loss reduction at High Frequency
>
> Hi Members,
>
> What are the methods by which we can reduce the conductor losses =
at=3D20
> high frequency?(Loss due to skin effect, Dielectric losses etc.) Which

> is the best conductor at higher frequency? in the range of 1-5 GHz
>
> Thanks,
> Sridhar
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