[SI-LIST] Re: on chip decoupling for Off chip drivers
- From: "Bradley S Henson" <bhenson@xxxxxxxxxxxxxxxxx>
- To: chris.cheng@xxxxxxxxxxxx
- Date: Thu, 21 Feb 2002 07:18:30 -0800
Chris Cheng
<chris.cheng@3pard To:
"'zabinski.patrick@xxxxxxxx'"
ata.com> <zabinski.patrick@xxxxxxxx>,
si-list@xxxxxxxxxxxxx
Sent by: cc:
si-list-bounce@fre Subject: [SI-LIST] Re: on
chip decoupling for Off
elists.org chip drivers
02/20/2002 09:09
PM
Please respond to
chris.cheng
***Snipped
Can someone explain to me why do we need 175pf per
driver to support a 50 ohm driver into a 50 ohm
transmission line load ?
Thanks,
Chris
-----Original Message-----
From: Zabinski, Patrick J. [mailto:zabinski.patrick@xxxxxxxx]
Sent: Wednesday, February 20, 2002 4:37 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: on chip decoupling for Off chip drivers
***Snipped
Chris,
This may help get your thinking aligned with Pat's response:
Let's use a 2.5V CMOS output. Switching this across a 50_ohm source
impedance and a 50_ohm line impedance would produce a power supply current
demand of 25mA. We want to keep the high frequency current demand caused by
the di/dt as local as possible. While some of the decoupling can come from
off-chip, it is not practical to decouple the fastest edge rates through
any significant distance and package inductance. Let's say we want to
decouple the 1st 1ns of the 25mA on chip. Using Pat's 10% ripple allowance:
Q=CV: it=CV
V=250mV (possibly misinterpreted, but OK for an example)
i=25mA
t=1ns
C= 100pf
So the highest frequencies of the switching edge will be treated by the
local 100pf, then the off-chip high frequency capacitance in the PWB and
small ceramics will source the lower di/dt current. Since the off chip
decoupling has a fairly large loop area, the effective inductance limits
the effectiveness of the remote caps for the fastest edge rates.
Since it is an example only, you can play with the assumptions. Some texts
use simple charge transfer between the decoupling and the load (load
treated as a lumped capacitor). This works too, albeit a bit dated for much
of what we do today like Gigabit I/O. You really need to use simulation
that includes the cascaded capacitances with their respective ESR/ESL and
the physical transmission-line that carries the power supply and decoupling
currents. The folks from Sun Micro (Larry Smith et all) have some nice
papers on decoupling and power/ground plane modeling.
Brad Henson
Raytheon
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