[SI-LIST] Re: on chip decoupling for Off chip drivers
- From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
- To: "'zabinski.patrick@xxxxxxxx'" <zabinski.patrick@xxxxxxxx>,si-list@xxxxxxxxxxxxx
- Date: Wed, 20 Feb 2002 21:09:59 -0800
Can someone explain to me why do we need 175pf per
driver to support a 50 ohm driver into a 50 ohm
transmission line load ?
Thanks,
Chris
-----Original Message-----
From: Zabinski, Patrick J. [mailto:zabinski.patrick@xxxxxxxx]
Sent: Wednesday, February 20, 2002 4:37 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: on chip decoupling for Off chip drivers
Himanshu,
I searched the literature about a year ago, and I
was not able to find anything.
In its place, we performed a simulation-based study to
determine how much on-chip decoupling was needed to
sufficiently decouple output drivers (full-swing CMOS
drivers with 50 ohm output impedance driving a 50
ohm transmission line into a high impedance load).
Using a criteria of 10% max ripple on the on-chip VDD
supply and including packaging parasitics (both signal
and power), we determined we needed roughly 175 pF per
output driver.
For reference, common CMOS technologies today offer about
5 fF/um^2 in gate capacitance (typically much higher than
MIM or well capacitance), so we needed about 175,000/5 =
35,000 um^2, or about 500 um by 70 um decoupling cap
area for each output driver. This is a tremendous amount
of real estate, so we opted to use a combination of
on-chip decoupling (for high-freq) and off-chip decoupling
(for low freq).
One interesting point to note: when we first got our simulations
to run, we had a rather large value inductor model for the
wire bonds, and the on-chip caps resonated with the wire
bonds at nearly the same frequency as our signals. It was
not a pretty site. We took the time (i.e., cost) to find
ways of shortening our wires and adding more of them to
reduce the inductance (i.e., push the resonant freq
up higher).
Pat
> Hello,
>
> I am looking for some literature on decoupling
> capacitor requirements for off-chip drivers. The
> decoupling capacitor is to be placed inside the CMOS
> chip.
>
> Any inputs will be appreciated.
>
> Thanks
>
> Himanshu Arora
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