[SI-LIST] Re: on chip decoupling ...

  • From: "Todd Westerhoff" <twester@xxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 21 Feb 2002 14:56:21 -0500

Okay, I'll bite.  This is one of Chris' absolute favorite subjects ....

We've become interested in modeling the decoupling/power distribution
behavior of different die/package/PCB configurations.  Admittedly a complex
problem, but an essential one nonetheless, lest any short-term transient
current demands that should have been satisfied on-die find their way out
onto the PCB ...

My question is - how are people modeling and analyzing this problem ... and,
how are they interpreting the results?  We have looked at a variety of
possible approaches in both the time and frequency domains, involving
various combinations of tools.  We're looking for an approach that will
allow us to model power delivery for complex ASIC/PCB configurations, that
can be performed within our lifetime and that don't require a Ph.D. to
understand (... as I don't have one!).

Bottom line - what are people doing today to address this issue, and what
approaches are you looking at for the future?

Comments (on and off the list) are always welcome and GREATLY appreciated.

Todd.

Todd Westerhoff
Signal Integrity Engineer
Hammerhead Networks
5 Federal Street - Billerica, MA - 01821
email:twester@xxxxxxxxxxx - ph: 978-671-5084
============================================

"Oh, but ain't that America, for you and me
 Ain't that America, we're something to see
 Ain't that America, Home of the Free
 Little pink houses, for you and me"

- John Mellencamp




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