[SI-LIST] Re: local and global ground
- From: Larry Smith <ldsmith@xxxxxxxxxxxxxxxxxx>
- To: perry.qu@xxxxxxxxxxx, ldsmith@xxxxxxxxxxxxxxxxxx,gedlund@xxxxxxxxxx
- Date: Mon, 4 Feb 2002 12:30:46 -0800 (PST)
Greg - I think your major point is that the 'ground' on one board jumps
400mV (40% of signal swing) compared to the ground on the other board.
This can happen. One time in the lab, I measured a 3 volt spike (5V
technology) in the 'ground' voltage across a rather poor connector for
the very same reason: too much inductance to support the di/dt. The
amazing thing is that the product was mostly working. This is the
classic SSN problem.
But in your case, you are only switching one driver. Watch out if you
have several signals switching simultaneously. The synchronous signals
(the ones with setup and hold time WRT the clock) will probably do ok.
But the asynchronous signals (the ones that are not latched with the
clock) are likely to be in trouble. And of course the clock is the
most important asynchronous signal. A glitch on the clock will really
mess up the system. Differential clocks are best.
One thing that is not very well modeled here is the capacitance of gnd
and gnd3 to the rest of the world. The spike that you get across
across a connector between two local grounds has a lot to do with both
the inductance between grounds and the capacitance between grounds.
That will help settle things down a little. Also, capacitance between
the signal and ground pins is important. Capacitance in this position
of the circuit turns inductance into impedance and delay. The more
distributed this capacitance is, the better.
But for the most part, the phenomenon you have identified is real.
Scary, isn't it. Use low inductance connectors and lots of ground
pins!
regards,
Larry Smith
Sun Microsystems
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> Subject: [SI-LIST] Re: local and global ground
> To: perry.qu@xxxxxxxxxxx, ldsmith@xxxxxxxxxxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> From: "Gregory R Edlund" <gedlund@xxxxxxxxxx>
> Date: Mon, 4 Feb 2002 12:48:25 -0600
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>
> Perry and Larry,
>
> I was out of town last week, so I didn't read your posts until Friday. I
> have struggled with simple power distribution models in an attempt to get
> my arms around what I know is a very complex problem. Like Perry, even my
> most simple simulations yield results that seem counter-intuitive to me,
> i.e. I know we pass power and signals through connectors and don't see
> anywhere near the amount of dv/dt noise my simulations predict. I read
> Larry's paper, "Simultaneous Switch Noise and Power Plane Bounce for CMOS
> Technology," which was encouraging because it solved a basic problem using
> a simple model with solid lab correlation.
>
> I am attaching a simulation deck that I think encapsulates the problem
> Perry posed. If you run it you will see a 400 mV peak on the local ground
> node. That's 4/10 of the signal swing! The connector inductance is about
> 15 nH, di = 20 mA, and dt = 0.5 ns. Therefore, v = L di/dt = 600 mV, which
> is in the ball park if this simple connector acts like a simple inductor.
> However, I think I can build this configuration and measure something much
> less than 400 mV, right? In my case, I'm not convinced it's numerical in
> nature. I'm guessing that there is something else going on in real life
> that I am not modeling.
>
> Anybody have some insight into this riddle?
>
> Greg Edlund
> Electronic Packaging & Integration
> IBM Server Technology Development
> 3605 Hwy. 52 N, Dept. HDC
> Rochester, MN 55901
> gedlund@xxxxxxxxxx
>
>
> Date: Mon, 28 Jan 2002 16:37:20 -0500
> From: "Perry Qu" <perry.qu@xxxxxxxxxxx>
> Subject: [SI-LIST] local and global ground
>
>
> Hi!
>
> I tried to do some simulation in HSPICE on module connectors connecting
> daughter card with the main board. There is one problem I encountered
> related to local ground and global ground node. Intuitively, I define the
> ground on the main board as node "0" in HSPICE. The input ground node of
> connector is tied to "0" through very small resistor. At the output side, I
> used a node "module_ground", which is linked with "0" on main board through
> connector model (parasitic RLCs). At the daughter card side, I then use
> this "module_ground" as the reference point for device, transmission line,
> etc. This actually simulate the real life and I expect to find out the
> noise on the "module_ground" due to inductive/resistive pins through
> connectors.
>
> However, in my simulation, I saw excessive noise (high frequency and large
> amplitude, which is definitely numerical noise rather than real thing)
> using connector model from one vendor, and I got error message as
> "inductor/voltage loop" using connector model from another vendor. By
> changing reference node on daughter card from "module_gnd" to "0", the
> error is gone. Wonder whether you have any experience to share on such
> problems, especially with HSPICE.
>
> Thanks
> Perry
>
> --
> Perry Qu
> Product Integrity | 600 March Road
> Alcatel Canada | Ottawa, ON K2K 2E6, Canada
> DID: (613) 7846720 | FAX: (613) 5993642
>
>
>
> * connector di/dt simulation
> * two pins from a straight-through header
> * pins are 0.5 x 0.5 mm each at 2.0 mm pitch
> * pin length = 20 mm
>
>
> * vsrc is a ramp function with rounded corners
>
> vsrc src gnd pwl
> + 0.00000000e-09 0.00000000e+00,
> + 1.00000000e-09 0.00000000e+00,
> + 1.00728536e-09 1.04749925e-03,
> + 1.01230955e-09 2.98950612e-03,
> + 1.01666498e-09 5.47700003e-03,
> + 1.02537584e-09 1.26837911e-02,
> + 1.04279745e-09 3.59374061e-02,
> + 1.07717645e-09 1.15284845e-01,
> + 1.11771131e-09 2.61263251e-01,
> + 1.15862179e-09 4.56881702e-01,
> + 1.20053422e-09 6.94177032e-01,
> + 1.24460769e-09 9.66125727e-01,
> + 1.29132187e-09 1.25672615e+00,
> + 1.32953060e-09 1.47916722e+00,
> + 1.34953058e-09 1.58539677e+00,
> + 1.37969661e-09 1.72766232e+00,
> + 1.44002855e-09 1.92984247e+00,
> + 1.48411775e-09 1.99502504e+00,
> + 1.50000000e-09 2.00000000e+00,
> + 2.00000000e-08 2.00000000e+00
>
>
> rsrc src sig1 50
>
> tline1 sig1 gnd sig2 gnd td=2ns z0=50
>
> xconn sig2 gnd sig3 gnd3 conn_2pin
>
> tline2 sig3 gnd3 sig4 gnd td=2ns z0=50
>
> rterm sig4 gnd 50
>
>
>
> *****************
> * SUBCIRCUITS *
> *****************
>
> .subckt conn_2pin pin1_in pin2_in pin1_out pin2_out
>
> c12a pin1_in pin2_in 0.1pF
>
> l1 pin1_in pin1_x 15.7nH
> r1 pin1_x pin1_out 0.01
>
> l2 pin2_in pin2_x 15.7nH
> r2 pin2_x pin2_out 0.01
>
> c12b pin1_out pin2_out 0.1pF
>
> k12 l1 l2 0.53
>
> .ends
>
>
> ******************
> * RUN CONTROLS *
> ******************
>
> .option post probe csdf
>
> .tran 20ps 10ns
>
> .probe v(src)
> .probe v(sig1) v(sig2) v(sig3) v(sig4)
> .probe v(gnd3)
>
> .end
>
>
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