Capacitance of parallel plates with dielectric is C = k E0 A / d
where E0 is the permittivity of space (close enough to air) which is
8.854e-12, k is dielectric constant (of FR4: about 4.5), A is Area of the
plates and d is separation between the plates.
So, how much area on two adjacent layers are you willing to devote to
this?
I'll pick a really large guess: how about a square 30cm on each side, so
the Area is 900 cm^2
I'll also be generous and say there are only 0.2mm between those planes.
So:
C = 4.5 * 8.845e-12 * 0.9m^2 / 2e-4 = 0.1793uF
thirty 0.22uF capacitors total 6.6uF.
SO, you need about 37 times more capacitance than a 30cm * 30cm square
with 0.2mm separation gives. You almost certainly don't have enough
layers or enough area to get there.
In short: no, the capacitance realized by embedding capacitance in the PCB
stackup can not (reasonably) replace thirty 0.22uF caps.
--- Joe S.
From: "Peterson, James F (Chief Engineers)"
<james.f.peterson@xxxxxxxxxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Date: 07/20/2016 02:51 PM
Subject: [SI-LIST] embedded capacitance for decoupling
Sent by: si-list-bounce@xxxxxxxxxxxxx
Can the capacitance realized by embedding capacitance in the PCB stackup
replace discrete decoupling capacitors?
Let's say the discrete decoupling solution for a processor's Vcore rail
has thirty 0.22 uf Hi-F caps. Is there a practical way to use an embedded
passives approach in the PCB stackup to achieve the needed decoupling
capacitance and thus remove these thirty discrete capacitors?
If so, are there any papers published around this? (I've searched and
can't find anything substantial on replacing discrete ceramic capacitors
with embedded PCB capacitance.)
Thanks,
Jim Peterson
Honeywell Aero
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