[SI-LIST] Re: Virtex -5 PCI ibis file and simulation
- From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 9 Jul 2008 11:58:29 -0400
Charlene, I have a few comments.
If you are using IBIS models, you should be afraid ... not that you indeed
have an SI problem, but that your simulation results are garbage. Many IBIS
datasheets ('models') are junk and cannot be trusted, unless you can
independently verify them for accuracy. A lot of IC designers throw
together IBIS models apparently because their boss told them to, and
especially when they are for generic interface I/Os such as PCI, no thought
is given to making them represent reality.
If you see exactly the same waveforms whether you use Vdd=3.3V or 3.0V, then
perhaps the simulator is faulty, because the L->H driven waveforms are
supposed to track the supply voltage, assuming that you are varying the
correct supply voltage or parameter that affects the model of the driver.
The characteristics inside an IBIS model are Vdd-relative, and you'd get no
waveform until the model knows what the Vdd is.
Presumably the negative overshoot limits your simulator is complaining about
are limits in the IBIS datasheet (model), which the IC vendor put there. If
you read the PCI spec, it says essentially that PCI devices are supposed to
withstand whatever overshoot stresses are placed on them; well maybe not
exactly, but pretty much so. There are DC min and max voltages but those
are not overshoot limits.
It is also possible that the Vertex or PPC devices are not PCI compliant,
despite claims made to that effect. Some IC vendors, even "respectable"
ones, are not trustworthy about making components that actually meet the
specs. Over the years I've seen a number of "PCI" ICs that can not possibly
meet the PCI requirements, according to their vendor's own published specs,
yet they lie and say they are compliant.
I've also had SPICE or IBIS models of "PCI compliant" devices that grossly
failed to meet the PCI specs, and when confronted with that fact, the vendor
altered the models to make them fit the PCI spec, offering no explanation!
Also I have had discussions with IC vendors who argued that their ICs could
not tolerate more than 0.1 or 0.2V of negative overshoot (what planet are
they from??), and vendors whose device models completely lacked negative
overshoot clamping. Almost all ICs have negative clamping, whether or not
by way of intentionally designed-in clamp diodes, but in SPICE models they
are frequently not modeled correctly, unless the person creating the model
knows enough about semiconductor physics. If your IBIS models came from
SPICE (as many do), that could cause them to be inaccurate.
Even though 33MHz PCI is relatively robust, a PCI bus can be a nasty
electrical environment. There tends to be a fair amount of overshoot in
both directions, when observed on the bus or at the IC pins. At the IC pads
it is probably better. If the V-5 devices are truly this sensitive to
negative overshoot, then perhaps they should not be used.
We commonly tell people that devices can be damaged over time, but to
be honest, I don't have evidence to support this. There is likely some
damage, I just don't know for sure that it stresses the part and leads to a
shortened lifetime (measured in years or months). I still believe that it
does.
It is puzzling that the overshoot you see in your simulations is independent
of trace length. Does at least the width of the overshoot pulse vary in
proportion to the trace length? It implies that the risetime of the driver
is a lot shorter than the electrical length of the traces ... and very fast
risetimes are not good.
Regards,
Andy
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