[SI-LIST] Re: Virtex -5 PCI ibis file and simulation

  • From: "Beal, Weston" <Weston_Beal@xxxxxxxxxx>
  • To: <crr1231@xxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 9 Jul 2008 16:29:02 -0700

 Charlene,

Thanks for sending the model files so that I could help answer your
questions. I created a simple point-to-point net in ICX and simulated
with the two models in question. Since the PPC file doesn't have a PCI
model I assume you are using the PCI-X model. That should be OK, but be
aware that PCI-X allows faster rise and fall times than standard PCI and
this model switches pretty fast (6V/ns in the model waveforms, not into
the specification load). On the Virtex side the PCI33 model has C_comp
of 6pF which seems a bit on the high side for a modern part, but I think
it's within the PCI specification.=20

I am suspicious of the PPC dynamic clamp in the PCI-X model.
Essentially, what it does is double the power and ground clamp strength
when the buffer is receiving. Does the datasheet of the part say that
this is the intended operation?

Here are a couple of things to experiment with to see how they affect
your circuit:
- adjust the C_comp value in the receiver model. Make it very small
(1pF) and very large (20pF) to see what it does to both the receiver and
driver waveforms. The reflections from the die capacitance do some
interesting things back at the driver.
- make the net much longer to separate out the reflections and study
them. Make the net longer again to see if the reflection moves where you
think it should.
- Widen the traces so that the trace impedance is 40, 30, or 20 Ohms.
See how that decreases the overshoot. The buffers are not well matched
to the desired 60 Ohms for PCI.

In summary, ICX is simulating the given models correctly and the
overshoot is controlled by the power and ground clamps of the driver and
receiver. As stated by others, PCI is rather noisy and the specification
allows for this and expects buffers to have clamps to control it.

If you have further questions about operation of ICX you can get great
support at=20
http://supportnet.mentor.com.

Regards,
Weston

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Beal, Weston
Sent: Wednesday, July 09, 2008 1:01 PM
To: crr1231@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Virtex -5 PCI ibis file and simulation

Charlene,

Another route to get some help on this is to get Mentor Graphics
customer support involved. We are familiar with ICX, IBIS and PCI. If
you can send me the design and the IBIS files, or just the IBIS files, I
can tell you if ICX is working properly, or if the models have problems,
or hopefully explain the results you see in ICX.

Regards,
Weston
weston_beal@xxxxxxxxxx




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of crr1231@xxxxxxx
Sent: Tuesday, July 08, 2008 5:23 PM
To: Aubrey_Sparkman@xxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Virtex -5 PCI ibis file and simulation

I am using PCI (33MHz). The simulator says that my problem is with
undershoot but I'm thinking that the model isn't very good. It is a
point to point trace and very short (PPC to V5). I don't have room on
the board for series resistors and don't realy want to go down that
path. I'm dissapointed that the simulator (ICX) and the ibs model for
the V5 is showing what it does. The only way I can reduce the undershoot
is to insert the V5 with a fast-6mA driver in place of the PPC IO. Any
other suggestions are welcomed.
Thanks,
Charlene


-----Original Message-----
From: Aubrey_Sparkman@xxxxxxxx
To: weirsi@xxxxxxxxxx; crr1231@xxxxxxx
Cc: si-list@xxxxxxxxxxxxx; cradtke@xxxxxxxxxxxxxxx
Sent: Tue, 8 Jul 2008 1:13 pm
Subject: [SI-LIST] Re: Virtex -5 PCI ibis file and simulation



Charlene,
You didn't say whether you were using PCI or PCI-X, but my memory says
both PCI and PCI-X specs allowed HUGE amounts of over and undershoot.
PCI-66 was often the worst case.  Are you sure you violate the *shoot
specs?  The spec allows so much, I've only ever seen this once.

Steve is right that series resistors can reduce the *shoots but that
takes a lot of resistors and they can kill your setup time if you have a
long link or several loads.


Aubrey Sparkman=3D3D20
Enterprise Engineering Signal Integrity Team=3D3D20 Dell, Inc.=3D3D20
Aubrey_Sparkman@xxxxxxxx=3D3D20
(512) 723-3592=3D3D20
"The single biggest problem in communication is the illusion that it has
taken place." -- George Bernard Shaw



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Tuesday, July 08, 2008 2:42 PM
To: crr1231@xxxxxxx
Cc: si-list@xxxxxxxxxxxxx; cradtke@xxxxxxxxxxxxxxx
Subject: [SI-LIST] Re: Virtex -5 PCI ibis file and simulation

PCI is so old that this could be a real problem.  I don't believe Xilinx
does anything to particularly slow down V5 outputs when set for PCI I/O.
External resistors should take care of the problem.


Steve.
crr1231@xxxxxxx wrote:
> I was wondering if anyone else in the community has been able to
implement (in simulation and in Hardware) PCI at 3.3v on the virtex 5
device (point to point between processer and FPGA). It seems that the V5
model that I am using responds the same whether I use 3.3V or 3.0V and
gives the same over and undershoot regardless of trace length using the
PCI models in the ibis file. According to my questionable simulations,
overshoot is within range but undershoot is out by 300mV. My concern is
that the sim is somewhat accurate, in hardware - the input diodes will
not be able to clamp and the device will be damaged (over time). If
anyone has successfully used an ibis model ( I am using the 1136
package), would you mind emailing it to me?
> With much appreciation,
> Charlene
>
>
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