[SI-LIST] Re: Virtex -5 PCI ibis file and simulation
- From: steve weir <weirsi@xxxxxxxxxx>
- To: crr1231@xxxxxxx
- Date: Wed, 09 Jul 2008 06:13:44 -0700
Charlene, if the trace is short, and the package capacitances aren't too
bad, then there isn't going to be a whole lot of stored energy. You
could get someone else to have a look at your simulation set-up, and/or
verify the models.
Steve.
crr1231@xxxxxxx wrote:
> I am using PCI (33MHz). The simulator says that my problem is with undershoot
> but I'm thinking that the model isn't very good. It is a point to point trace
> and very short (PPC to V5). I don't have room on the board for series
> resistors and don't realy want to go down that path. I'm dissapointed that
> the simulator (ICX) and the ibs model for the V5 is showing what it does. The
> only way I can reduce the undershoot is to insert the V5 with a fast-6mA
> driver in place of the PPC IO. Any other suggestions are welcomed.
> Thanks,
> Charlene
>
>
> -----Original Message-----
> From: Aubrey_Sparkman@xxxxxxxx
> To: weirsi@xxxxxxxxxx; crr1231@xxxxxxx
> Cc: si-list@xxxxxxxxxxxxx; cradtke@xxxxxxxxxxxxxxx
> Sent: Tue, 8 Jul 2008 1:13 pm
> Subject: [SI-LIST] Re: Virtex -5 PCI ibis file and simulation
>
>
>
> Charlene,
> You didn't say whether you were using PCI or PCI-X, but my memory says
> both PCI and PCI-X specs allowed HUGE amounts of over and undershoot.
> PCI-66 was often the worst case. Are you sure you violate the *shoot
> specs? The spec allows so much, I've only ever seen this once.
>
> Steve is right that series resistors can reduce the *shoots but that
> takes a lot of resistors and they can kill your setup time if you have a
> long link or several loads.
>
>
> Aubrey Sparkman=20
> Enterprise Engineering Signal Integrity Team=20
> Dell, Inc.=20
> Aubrey_Sparkman@xxxxxxxx=20
> (512) 723-3592=20
> "The single biggest problem in communication is the illusion that it has
> taken place." -- George Bernard Shaw
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of steve weir
> Sent: Tuesday, July 08, 2008 2:42 PM
> To: crr1231@xxxxxxx
> Cc: si-list@xxxxxxxxxxxxx; cradtke@xxxxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Virtex -5 PCI ibis file and simulation
>
> PCI is so old that this could be a real problem. I don't believe Xilinx
> does anything to particularly slow down V5 outputs when set for PCI I/O.
> External resistors should take care of the problem.
>
>
> Steve.
> crr1231@xxxxxxx wrote:
>
>> I was wondering if anyone else in the community has been able to
>>
> implement (in simulation and in Hardware) PCI at 3.3v on the virtex 5
> device (point to point between processer and FPGA). It seems that the V5
> model that I am using responds the same whether I use 3.3V or 3.0V and
> gives the same over and undershoot regardless of trace length using the
> PCI models in the ibis file. According to my questionable simulations,
> overshoot is within range but undershoot is out by 300mV. My concern is
> that the sim is somewhat accurate, in hardware - the input diodes will
> not be able to clamp and the device will be damaged (over time). If
> anyone has successfully used an ibis model ( I am using the 1136
> package), would you mind emailing it to me?
>
>> With much appreciation,
>> Charlene
>>
>>
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