Good SI work is all about minimizing the effort and maximizing the
results. All SI effort based on post-layout simulation is very time-
consuming and huge amount of effort. All assessment based on pre-layout
work is a good risk because lot depends on skills of layout engineer. He
may minimize effort of SI engineer or just create enormous amount of
post-layout work for SI engineer.
Therefore, it is highly recommended to follow mix of prelayout and
postlayout approach. channel can be broken into number of segments.
critical segment of channel can be modeled as post-layout and model other
segments as prelayout. These prelayout segment would normally need good
number parametric variation for certain parameter conclusion (e.g. channel
length etc..). This approach can ensure good results within minimum
possible time-frame. Final layout verification definitively would
definitely need one or two spot-check postlayout SI simulations for full
channel. This is for SI.
There is no concept of prelayout work for power integrity, Although some
people follow their own prelayout flow. it is better to run DC, AC and
decap analysis on real layout file. Power integrity postlayout work is
usually not very time consuming
In summary, it all depends on specific package/board layout, specification
requirements and judgement of SI engineer. script based automation
environment can hugely minimize the effort and can add great value/insight
to the results.
Although cost of PCB iteration is small. But in reality.. nobody like to
see any kind of failure and delay the schedule.
Thanks
Sanjeev Gupta
www.sigintegrity-solutions.com
On Thu, May 4, 2017 at 7:01 PM, David Banas <dbanas@xxxxxxxxx> wrote:
Hi Carson,
Given that complete interface validation (i.e. - from extraction to timing
report) now takes less than a day, the cost of doing it, in both hours and
dollars, is quite low compared to a board respin. So, we always do it,
before releasing our Gerbers for fabrication. And we almost always find
things that need a little tweaking.
-db
On May 4, 2017, at 3:49 AM, Carson Au <carson.au@xxxxxxxxx> wrote:
Hi Experts,
How much of your simulation work for SERDES channel designs on PCBs are
pre-layout, and how much is your work post-layout?
Do post-layout simulations add much value to your design process? If you
come up with a robust set of design rules from pre-layout simulation
exploration work, and you adhere to these design rules in layout, there
should not be all that much additional value in post-layout simulations?
Regards,
Carson
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