[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator
- From: "Istvan NOVAK" <istvan.novak@xxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>, <fred@xxxxxxxxxxxxx>
- Date: Mon, 11 Aug 2003 21:42:02 -0400
Fred, Peter,
You are correct, as always, it depends. For people who might be familiar
from their experience mostly with only one or the other extreme scenario,
let
me summarize briefly the situation.
Though it was not specifically mentioned, everyone on this thread assumed
(or I think so) that the bypass capacitors are connected to planes (as
opposed
to the smallest possible power patch, when we cant speak about distance,
because there is just an active device with a few capacitors around it on
the
patch). It is usually agreed that at low frequencies, the location of
capacitor
does not matter much. So bulk capacitors could be excluded from the
discussion, though it is easy to show that we can always find an exception
if we want to: imagine the bulk capacitors that have their series
resonance frequencies in the 100kHz-1MHz range. The wavelength is very long
compared to any practical PCB size, and still, it may be a good idea to put
the
bulk capacitors close to the output of the DC-DC converter, otherwise the
switching ripple current (in the other of a few hundred kHz) will have to
travel
all over the board and would spread the switching ripple.
At higher frequencies, the location of capacitors MAY matter. It depends on
the
impedance ratio of planes and capacitors. Similar to a matching resistor
for a
trace, when the impedance values agree or are close, the setup becomes
increasingly
insensitive to the geometry and relative locations. If we terminate the end
of a trace
properly, the input impedance on a low-loss trace is always the
characteristic
impedance, regardless where we are along the trace. Same applies in two
dimensions
to planes: if the impedance of the planes is close to our required PDN
impedance,
component locations matter very little as long as we provide a matched
termination to
the planes.
The capacitor location increasingly matters as soon as we cannot or
do not want to use matched planes: either the impedance requirement might be
so
low that it cannot be easily provided by (matched) planes, or we do not have
the
proper components to provide the plane matching. As the ratio of plane
impedance
and capacitor ESR increase, there is an increasing sensitivity to component
location.
The typical scenario is that the plane impedance is high and the ESR is low.
This is
similar to having a shorted trace: the input impedance is a strong function
of distance
even at very low frequencies. If we keep the proper distance from the active
device, our impedance target still can be met. Capacitor-plane resonance
will build
up, but as long as we dont excite them, it is OK.
Dependent on system considerations (determining our particular impedance
target),
available components, cost and manufacturing constraints, we may have one or
the
other extreme, or anything in between. All of the comments leaning one way
or
the other on this thread are correct within their validity range. We have
designs
embracing the full range explained above, we built and measured them.
This thread started out with the posting about the UltraCAD tool. It is a
matter of
preference to use expression solvers (like the UltraCAD tool, or a
spreadsheet, or
a MATHCAD file) or a simulator (SPICE or alike). I use several different
options,
Berkeley SPICE, PSPICE, HSPICE, spreadsheets and scripts based on analytical
expressions. All have their particular sweet spot of usage. SPICE can run
fast, but
it is easier to use an expression solver to simulate a full impedance
surface, which
can be set to step through a range of frequencies and display the changing
impedance
surface of a plane with a bypass capacitor at an arbitrarily specified
location. Such
a spreadsheet will be available for free download in the near future: send
me an off-line
mail if you are interested. Notification is sent out only to those, who ask
for the
e-mail notification.
Best regards,
Istvan Novak
SUN Microsystems
----- Original Message -----
From: "Fred Balistreri" <fred@xxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Monday, August 11, 2003 6:21 PM
Subject: [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator
> I believe the condradictions start when we generalize. Every design
> is different and the solutions for one do not necessarily apply to
> another. But we should be able to agree on the basic concepts and
> come to understand what the assumptions are when statements are made.
>
> Best Regards,
>
> Peter Arnold wrote:
> >
> > All,
> >
> > I am not sure there should be so much controversy over this placement
thing.
> > Among the conclusion in the UMR paper that I have a copy of [1] is this
> > assertion: "...all decoupling capacitors are shared in the frequency
range
> > where they are effective (typically below 200-300MHz), and the location
of a
> > decoupling capcitor on the board is relatively unimportant."
> >
> > The "unimportant placement" claim is made dependent on the condition
that
> > the caps, as mounted, are ineffective above 200MHz. At this frequency an
> > 8"x9" test board is electrically small with respect to 200MHz wavelength
in
> > FR4 (30") and the paper reports placement not to be crucial in
determining
> > impedance.
> >
> > I think this electrical-smallness, and taking capacitor mounting
inductance
> > at 2-10nH to be >> plane inductance between parts, is what prompts them
to
> > simplify the power delivery model to a network connected between two
spice
> > nodes as if all components were physically at the same place. Analyzing
this
> > the authors identify a frequency "fa" lying between the last zero and
the
> > last pole of the impedance plot above which the decouplers are
ineffective.
> > If this frequency is low as in the examples given, then cap placement
might
> > well not matter.
> >
> > But designs today do not necessarily support the simplification given
above.
> > Modern techniques like via-in-pad, multiple fanouts, "broadside" case
> > connections etc. reduce mounted inductance to 1nH or less per part. This
> > should allow mounted capacitors to be effective at higher frequencies
where
> > wavelengths are only a few inches and the board is no longer
electrically
> > small. At this point the everything-between-two-nodes and
> > no-inductance-in-series-with-plane-capacitance simplification may not
hold
> > and a bedspring-type model would be needed. Decoupler placement may then
> > become important (as experience appears to confirm!) This does not
> > contradict the UMR authors' statement, which relates to a
> > high-mounted-inductance regime and frequencies below 200MHz on a small
> > board.
> >
> > Can anyone comment?
> >
> > [1] Hubing et al., "Power Bus decoupling on Multilayer Printed Circuit
> > Boards," in IEEE trans. EMC vol 37, no. 2, May 1995.
> >
> > Regards,
> > peter arnold.
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ray Anderson
> > Sent: Monday, August 11, 2003 9:36 AM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator
> >
> > Lee Ritchey wrote:
> > > If the location of decoupling capacitors matters, perhaps some
technical
> > > demonstration would prove that. Short of such a demonstration, this
is
> > > speculation and not the sort of thing that should be used to make
design
> > > choices.
> > >
> > > It's time to do some good engineering on this subject and do away with
> > > opinion. The UMR paper is good engineering. Anyone who chooses to
> > > disagree with it has the burden of showing where it is wrong by using
some
> > > good science.
> > >
> > > Lee
> > >
> > > Lee Ritchey
> > > leeritchey@xxxxxxxxxxxxx
> > > Why Wait? Move to EarthLink.
> >
> > Or conversely, show that it doesn't matter.
> >
> > Take a large system board (say about 24" square) put a bunch of high
current
> > processors and ASICS on the left side of the board. Put all your decaps
> > on the right side of the board (since you maintain position doesn't
matter).
> >
> > In this hypothetical case I can just about guarantee the board won't
> > function
> > properly or pass EMI. Admittedly, it is a contrived case, but I think it
> > illustrates the point.
> >
> > As far as the technical demonstration goes, we have indeed demonstrated
to
> > ourselves that position does matter.
> >
> > I'm not attempting to further an argument, but I do feel those who have
> > responded with viewpoints other than yours shouldn't be chastised and
> > accused
> > of spreading unfounded opinion. Don't discount the chance that an
opinion
> > that
> > differs from yours just might be correct.
> >
> > -Ray Anderson
> > Sun Microsystems Inc.
> >
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>
> --
> Fred Balistreri
> fred@xxxxxxxxxxxxx
>
> http://www.apsimtech.com
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