[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator
- From: "Vishram Pandit" <vishrampandit@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 06 Aug 2003 13:44:53 +0000
In my experience, location of the caps play VERY IMPORTANT role in the EMI.
The capacitors are placed near the chip as well as on the "hot spots". PDS
impedance response is analyzed and the value of the capacitors is
determined.One of the major contributor to the EMI is edge radiation which
isclosely coupled to PDS response. We have seen significant improvment in
theEMI by optimizing:
1] Location of caps
2] Value of caps
3] ESR / ESL of caps
The caps are placed in between power and ground at various "hot spots"
including edge of the board, edge of the power planes, etc. I am not sure
howto determine the target PDS impedance response say up to 2GHz. What
factors affect it and what should be the goal? I have seen boards with
higherimpedance (say 20 Ohms at 800MHz) passing and with lower impedance (
say 5 Ohms) failing. In the latter case, we have to lower it more (1 Ohm)
and that improved the EMI. Any advice on this??
Thanks,
Vishram >From: Larry Smith >Reply-To: si-list@xxxxxxxxxxxxx >To:
si-list@xxxxxxxxxxxxx >Subject: [SI-LIST] Re: UltraCAD ESR and Bypass
Capacitor Caculator >Date: Mon, 4 Aug 2003 09:10:14 -0700 (PDT) >>Robert -
Let me address the subject of capacitor placement with a quick >war story.
Several years ago, we were having an EMI problem at about >900 MHz. We
determined the capacitor value that made a low impedance >at that frequency
while mounted on our power planes, I think it was >about 27pF or so. We
placed several of them on the PCB just a few >inches away from our
microprocessor in the decoupling pad sites that >were available. The result
was that EMI at 900 MHz got worse! Some >simple calculations showed why. We
had placed relatively low impedance >capacitors 1/4 wavelength from the
source. Because of transmission >line phenomenon, a low impedance becomes a
high impedance 1/4 >wavelength away. This was in the very early days of
powerplane >modeling. Our primitive power plane models predicted this effect
quite >nicely. That convinced us that we had to use PDS tools to place caps
>that resonate at frequencies that translate to wavelengths that are
>comparable to the PCB size. >>That was back in the days when we used power
and ground planes spaced >about 14 mils apart with two signal layers
in-between. Since then, we >have learned the value of thin power plane
dielectrics and always place >power and ground planes next to each other in
the stackup, somewhere >between 2 and 4 mils apart. This has a number of
advantages including >increased capacitance between planes, lower spreading
inductance, lower >power plane impedance, increased noise damping and better
return path >for high frequency signals traveling in reference to those
planes. >Several papers have been written from authors at Sun which fully
>describe this. Many EMI problems have been solved by thin power plane
>dielectrics. >>With a good power plane stackup, it may not be necessary to
use many >(or any..) capacitors below 1000pF. As Ray mentioned below, the
power >integrity problem is usually limited to less than 100 MHz by the chip
>package inductance. If it is still necessary to use low valued >capacitors
for the signal integrity (return current) or EMI problems, >then position on
the power plane does become an important issue. >>regards, >Larry Smith >Sun
Microsystems >>>Delivered-To: si-list@xxxxxxxxxxxxx >>From: "Robert Sefton"
>>To: >>Subject: [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator
>>Date: Sun, 3 Aug 2003 10:27:54 -0700 >>MIME-Version: 1.0
>>Content-Transfer-Encoding: 8bit >>X-Priority: 3 >>X-MSMail-Priority:
Normal>>X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1165
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>>X-original-sender: rsefton@xxxxxxxxxxxxx >>X-list: si-list >>>>Ray -
>>>>5.5" is a pretty loose requirement. That seems consistent with >>Lee's
(and UMR's) statement that "location of the capacitors is >>relatively
unimportant" for decoupling. But what about EMI? Does >>placing the decaps
closer help with EMI, even if it doesn't >>improve the PDS performance?
Doesn't seem like it would. >>>>Thanks, >>Robert >>>>----- Original Message
----- >>From: "Ray Anderson" >>To: >>Sent: Friday, August 01, 2003 12:50 PM
>>Subject: [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator
>>>>>>>With all due respect to the UMR authors, I think the location >>>of a
decap on a set of power planes DOES matter. >>>>>>There is an inherent time
delay associated with the current flow >>>from the location where a decap is
placed to the location where >>the >>>chip to bypassed is located. >>>>>>The
decaps job is to provide current to the load quickly enough >>>that a
voltagecollapse on the planes doesn't occur. If the >>decap >>>is too far
away from the current consuming load it is possible >>>that load's need for
apulse of current will be over before the >>>current can get there. >>>>>>At
low frequencies you can place a decap just about anywhere on >>a plane
>>>andit will function just fine. At higher frequencies the decap >>must
>>>be closer to the device to be bypassed. The concept of >>"effective
bypassing >>>radius" says that a decap must be within say 1/6 to 1/10
>>wavelength >>>at the frequency of interest to be effective. (the exact
number >>is >>>debatable). The frequency of interest is the resonant
frequency >>of >>>the mounted decap (where the caps ESR is lowest), and the
>>distance is >>>a function of the speed of propagation with a given
dielectric >>between >>>the planes (around 180ps/inch for FR4). >>>>>>You
need to consider the role each component of a PDS (power >>distribution
>>>system) plays in maintaining a low impedance across a wide >>bandwidth.
>>>A typical PDS is composed of a VRM, bulk capacitors, ceramic >>decaps,
and>>>the power planes and last but not least the package housing the
>>silicon. >>>>>>The VRM provides a low impedance from DC to perhaps a few
>>hundred kHz, >>>the bulk capacitors contribute their impedance profile
froma >>few >>>hundred kHz up to about a MHz. From a Mhz to maybe 120MHz or
so >>the >>>ceramic decoupling caps provide low impedance. Above that
>>frequency >>>the distributed capacitance provided by the planes provides
the >>requisite >>>low impedance to the PDS. When the individual impedance
profiles >>of >>>each of the constituent parts are superimposed, the
resulting >>composite >>>profile provides a low impedance over the full
frequency range >>that the >>>PDS was designed for. Note that above the
package resonance >>frequency >>>(which usually is from about 50 to 100 MHz
for typical packages) >>decoupling >>>on the board is ineffective and the
necessary decoupling must be >>provided >>>for either in the package or on
the silicon. However, at >>frequencies >>>above the package resonance
frequency the discrete decaps and >>distributed >>>plane capacitance can be
most useful for EMI purposes. >>>>>>To summarize, at low frequencies, the
decoupling capacitors can >>be placed >>>almost anywhere withing reason and
will be effective. As the >>frequency >>>of interest increases, the
allowabledistance decreases. As an >>example, >>>at 1 MHz the wavelength (on
FR4) is around 214 meters. So >>lambda/10 is >>>around 21 meters. Hence, if
your decap which is effective at 1 >>MHz is >>>within 21 meters of the
consuming device, then the decoupling >>will be >>>effective. Conversely, if
you are trying to decouple at device >>with >>>a decap that is effective at
say 100 MHz then the wavelength of >>interest >>>is about 1.4 meters.
Lambda/10 is then .14 meters (approx 5.5 >>inches). >>>In this case if the
decap is appreciably more than 5.5 inches >>from the >>>currewnt consumer
then the delay will be such that the decap >>will not be able to >>>provide
current quickly enough to be effective. >>>>>>-Ray Anderson >>>Sun
Microsystems Inc. >>>>>>>>>Lee Ritchey wrote: >>>>>If you remember the UMR
paper on power bus decoupling, it >>made a clear case >>>>>that the location
of the capacitors is relatively >>unimportant.
>>>>>>>>>------------------------------------------------------------------
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