[SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator
- From: "FLOWERDEW, Peter" <peter.flowerdew@xxxxxxxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 11 Aug 2003 16:58:33 +0100
If the interaction of every variable that has an effect can be precisely
specified then one is in the realm of pure science. Otherwise one is in the
realm of engineering which includes elements of creativity and making
judgements in the face of insufficient data or inadequate tools or
insufficient time for rigorous analysis. That it why engineering is applied
science and requires artistry as well as science. 'Opinions' are usually
based on many 'unplanned experiments' as Mr Faraday called them. That is
what is now termed 'experience'.
By the way, invention and synthesis, central to design, are different
processes than analysis and require a different mindset and set of skills.
Hence many good graduates make poor designers.
Peter Flowerdew PhD CEng FIEE
Father to two First Class Oxford physics students (post and undergraduates)
and defender of creativity and simplicity.
Own opinions only. With no implication that other opinions also have
validity to those who love them.
-----Original Message-----
From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]
Sent: 11 August 2003 16:28
To: si-list@xxxxxxxxxxxxx; Raj Raghuram
Subject: [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator
Why are we basing engineering decisions on opinion? This isn't politics,
it's engineering and is based on science.
Lee Ritchey
leeritchey@xxxxxxxxxxxxx
Why Wait? Move to EarthLink.
> [Original Message]
> From: Raj Raghuram <raj.raghuram@xxxxxxxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Date: 8/4/2003 8:02:35 AM
> Subject: [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator
>
> Another opininon on this I have heard is that at higher frequencies, it
> is the decoupling on the package and IC that really matter. The package
> decap can have lower inductance and the IC decap almost negligible
> inductance. Unfortunately, the system level designer is often not privy
> to information on these decaps, especially the on-chip decap. All he has
> is the IBIS model which is made assuming ideal supplies. IC
> manufacturers need to provide some information about on-chip decoupling.
> Some opinions I have heard from designers on this are:
>
> 1. A profile of the current drawn by the IC is really needed for
> effective PDS design.
>
> 2. If there is on-chip cap deliberately added, this needs to be
> mentioned somewhere in the data or IBIS model.
>
> 3. Often there are a number of gates not switching. Each one has some
> capacitance between power and ground. The sum of these can be a
> significant source of decoupling, whether intended as such or not.
>
> 4. Issues such as whether on chip core supply is the same as the IO,
> etc. become important if on-chip decoupling is to considered.
>
> Ray Anderson wrote:
>
> >With all due respect to the UMR authors, I think the location
> >of a decap on a set of power planes DOES matter.
> >
> >There is an inherent time delay associated with the current flow
> >from the location where a decap is placed to the location where the
> >chip to bypassed is located.
> >
> >The decaps job is to provide current to the load quickly enough
> >that a voltage collapse on the planes doesn't occur. If the decap
> >is too far away from the current consuming load it is possible
> >that load's need for a pulse of current will be over before the
> >current can get there.
> >
> >At low frequencies you can place a decap just about anywhere on a plane
> >and it will function just fine. At higher frequencies the decap must
> >be closer to the device to be bypassed. The concept of "effective
bypassing
> >radius" says that a decap must be within say 1/6 to 1/10 wavelength
> >at the frequency of interest to be effective. (the exact number is
> >debatable). The frequency of interest is the resonant frequency of
> >the mounted decap (where the caps ESR is lowest), and the distance is
> >a function of the speed of propagation with a given dielectric between
> >the planes (around 180ps/inch for FR4).
> >
> >You need to consider the role each component of a PDS (power distribution
> >system) plays in maintaining a low impedance across a wide bandwidth.
> >A typical PDS is composed of a VRM, bulk capacitors, ceramic decaps, and
> >the power planes and last but not least the package housing the silicon.
> >
> >The VRM provides a low impedance from DC to perhaps a few hundred kHz,
> >the bulk capacitors contribute their impedance profile from a few
> >hundred kHz up to about a MHz. From a Mhz to maybe 120MHz or so the
> >ceramic decoupling caps provide low impedance. Above that frequency
> >the distributed capacitance provided by the planes provides the requisite
> >low impedance to the PDS. When the individual impedance profiles of
> >each of the constituent parts are superimposed, the resulting composite
> >profile provides a low impedance over the full frequency range that the
> >PDS was designed for. Note that above the package resonance frequency
> >(which usually is from about 50 to 100 MHz for typical packages)
decoupling
> >on the board is ineffective and the necessary decoupling must be provided
> >for either in the package or on the silicon. However, at frequencies
> >above the package resonance frequency the discrete decaps and distributed
> >plane capacitance can be most useful for EMI purposes.
> >
> >To summarize, at low frequencies, the decoupling capacitors can be placed
> >almost anywhere withing reason and will be effective. As the frequency
> >of interest increases, the allowable distance decreases. As an example,
> >at 1 MHz the wavelength (on FR4) is around 214 meters. So lambda/10 is
> >around 21 meters. Hence, if your decap which is effective at 1 MHz is
> >within 21 meters of the consuming device, then the decoupling will be
> >effective. Conversely, if you are trying to decouple at device with
> >a decap that is effective at say 100 MHz then the wavelength of interest
> >is about 1.4 meters. Lambda/10 is then .14 meters (approx 5.5 inches).
> >In this case if the decap is appreciably more than 5.5 inches from the
> >currewnt consumer then the delay will be such that the decap will not be
able to
> >provide current quickly enough to be effective.
> >
> >-Ray Anderson
> >Sun Microsystems Inc.
> >
> >
> >Lee Ritchey wrote:
> >
> >
> >>>If you remember the UMR paper on power bus decoupling, it made a clear
case
> >>>that the location of the capacitors is relatively unimportant.
> >>>
> >>>
> >
> >
> >Abe Riazi wrote:
> >
> >
> >>To be fair, it should be added that different recommendations ( from
above)
> >>
> >>
> >exist in literature
> >
> >
> >>regarding optimum location of the decoupling caps.
> >>
> >>Two examples follow:
> >>
> >>1. Stephen H.Hall et al., " High-Speed Digital System Design........",
on page
> >>
> >>
> >247 it is stated:
> >
> >
> >>" Figure 10.10 suggests not only that the local decoupling capacitor
value
> >>
> >>
> >should be chosen
> >
> >
> >>appropriately but that the capacitor is placed physically close to the
> >>
> >>
> >component to minimize
> >
> >
> >>the loop area ".
> >>
> >>2. A technical paper by R. Chen, "Where to Place Decoupling
Capacitors?..."
> >>
> >>
> >available on
> >
> >
> >>www.sigrity.com web site, implies that the best location for decoupling
caps
> >>
> >>
> >needs to
> >
> >
> >>be ascertained with aid of electromagnetic field simulation.
> >>
> >>Best Regards,
> >>
> >>Abe Riazi
> >>ServerWorks
> >>
> >>
> >
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> >
> >
>
> --
> Raj Raghuram
> Berkeley Design Automation (http://berkeley-da.com)
> 2902 Stender Way,
> Santa Clara, CA-95054
> PH: (408)-496-6600 ext.203
> Cell: (408)-390-7614
> EMAIL: raj.raghuram@xxxxxxxxxxxxxxx
>
>
>
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