[SI-LIST] Re: To remove reference planes under the gold finger areas
- From: steve weir <weirsi@xxxxxxxxxx>
- To: jeff.loyer@xxxxxxxxx, <kalevi@xxxxxxxxxx>, <Cortex.Chen@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 16 Jun 2005 07:58:28 -0700
Jeff, I agree that big pads translate to significant capacitance and
without compensation, impedance dips. But I am quite wary of your blanket
statement declaring no increase in crosstalk when we alter the image
plane. To believe that, I would have to think either that there is another
path(s) back to the original return that does not involve nearby signal
traces, or that the path was already so badly disrutpted by other problems
that the crosstalk just can't get much worse. Do you see something different?
Steve.
At 02:49 PM 6/15/2005 -0700, Loyer, Jeff wrote:
>This agrees with my knowledge/experience. Big pads look like WIDE =
>traces which equals very low impedance, compared to 50ohm traces. Some =
>of that can be reduced by trimming back the ground plane below the pads. =
> Experiments showed no increase in crosstalk with the ground planes =
>trimmed back.
>
>Jeff Loyer
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
>On Behalf Of Kai Keskinen
>Sent: Wednesday, June 15, 2005 1:39 PM
>To: Cortex.Chen@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: To remove reference planes under the gold finger =
>areas
>
>I would think it is to reduce the capacitance so that the signals don't =
>see
>a big localized impedance change.
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Cortex Chen
>Sent: Wednesday, June 15, 2005 12:17 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] To remove reference planes under the gold finger
>areas
>
>
>Dear SI experts,
>I'm working to design a FB-DIMM add-in card. To recall previous =
>experiences
>for PCI-E, I'm confused why it's recommended to remove reference planes
>under the gold finger areas of an add-in card. In detail, refer to =
>section
>2.3.2.6 (page 28 ~ 29) of PCI Express Design Guide (rev. no, 0.5, =
>12978).
>Who can tell me what the main reason is?
>
>By the way, refer to section 6.11.10 (page 417 ~ 418) from Howard =
>Johnson's
>new book, I like to quote some sentences for your reference as below:
>"......In a differential-pcb pair, most of the returning current from =
>each
>trace still flows on the solid plane, not the other trace, because each
>differential trace couples much more strongly to the big, solid nearby =
>plane
>than it does to its little, skinny differential buddy....".
>
>If it's true, then it will cause some effects like "Differential =
>U-Turn"?
>Please give me your comments.
>
>Thanks & Sincerely
>
> Cortex Chen =B3=AF=A5=C3=AAN
>
>
>
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