[SI-LIST] Re: The necessity of Pull-up resistors in DDR2
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: Hirshtal Itzhak <ihirshtal@xxxxxxxxxx>
- Date: Sun, 31 Jan 2010 15:07:13 +0100
Hi Itzhak,
The reason why I was confused regarding Pull up/ Pull down is because
you can also use a thevenin termination with one Pull up and one pull
down (causeing some crosscurrent).
So far I have not seen Bills e-mail (not sure why).
In the case of a floating bus I do not see a big issue. Your SI
simulations seem to indicate, that the system can handle the full swing
(GND to VDD) (sorry, in the previous mail I wrote VDDQ/VSSQ .. for CA
this is of course VDD and VSS). If the bus is terminated to VTT and not
driven it will settle to VTT. So for the first bit the required risetime
to reach high or low is a bit lower and therefore usually this results
in a improved setup time for the first bit after a time where the bus
was not driven.
In case of a floating bus the level can shift to high or low. But as
long as the level is between VSS and VDD this is basically covered by
your simulation.
Question would be if the level on the floating bus can drop below VSS or
rise above VDD ...
Hermann
Visit us on Embedded World 2010, 2. - 4. March 2010 in Nuernberg
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Hermann Ruckerbauer
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schrieb Hirshtal Itzhak:
>
> Hello Hermann
>
>
>
> My use of VTT stems from the SSTL18 protocol, where 1 of the
> termination options there is connecting RT to VTT (see Fig. 3 in
> JESD8-15a) at the receiver end of the line.
>
>
>
> You're right about the dynamic and DC current -- I've confused them.
>
>
>
> Don't you think there might be a problem when the bus is floating? See
> Bill Grenoble's response
>
>
>
> Thanks
>
>
>
> Itzhak Hirhtal
>
>
>
>
>
> ------------------------------------------------------------------------
>
> *From:* Hermann Ruckerbauer [mailto:hermann.ruckerbauer@xxxxxxxxxxxxx]
> *Sent:* Sunday, January 31, 2010 3:31 PM
> *To:* si-list@xxxxxxxxxxxxx; Hirshtal Itzhak
> *Subject:* Re: [SI-LIST] The necessity of Pull-up resistors in DDR2
>
>
>
> Hello Itzhak,
>
> not sure if I use pull up in the same way you do ..
>
> The definition I know is that a "Pull up" would terminate to VDDQ (and
> a "Pull down" terminate to VSSQ).
> It seems that you terminate to VTT what does not have a real name in
> my wording :-) (maybe "pull mid" ?)
>
> Of course you can run a DDR2 CA bus without termination.
> If the SI Simulation is shwoing a result that fulfills alls input
> parameters of the DRAM (Setup/Hold, slew rates, ringbacks, ..) there
> is no reason to use a termination.
> You need to take a close look to overshoots (and undershoots), as
> this one of the most critical things when using a rail to rail
> signaling with no termination.
> When this lines are terminated e. g. the high level is not reaching
> VDDQ and therefor even an overshoot over the high level is not a
> problem. If there is no termination the high level = VDDQ and
> therefore an overshoot can cause trouble.
> But basically this is part of the comment "if the SI simulations
> result fulfills input parameter requirement"
>
> but I do not understand the comment on dynamic current. The situation
> is quite similar that the dynamic current need to load the
> capacitances on the bus. The difference is the DC current that is
> missing in the system without termination.
>
> The improvement in Power and the lower component cost is maybe not the
> factor to do such a design, but the big advantage is the real estate
> on the board that is gained.
>
> Hermann
>
>
>
> Visit us on Embedded World 2010, 2. - 4. March 2010 in Nuernberg
> Follow our presentation on Tuesday, March 2nd, 11:00 a.m.
> "Signal Integrity in embedded computer systems"
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de <http://www.EyeKnowHow.de>
> Hermann.Ruckerbauer@xxxxxxxxxxxxx <mailto:Hermann.Ruckerbauer@xxxxxxxxxxxxx>
> Veilchenstrasse 1
> 94554 Moos
> Tel.: +49 (0)9938 / 902 083
> Mobile: +49 (0)176 / 787 787 77
> Fax: +49 (0)3212 / 121 9008
>
>
> schrieb Hirshtal Itzhak:
>
> Hello SI Experts
>
>
> I've conducted some pre-layout simulations on a DDR2 bus connected to
> on-board DDR2 devices.
>
>
>
> I found out that I get proper waveforms even if I don't use pull-up
> resistors on the Address & Control lines.
>
>
>
> I wonder if this is an acceptable result! I've always been using those
> pull-up resistors in previous designs.
>
>
>
> Is it a mandatory requirement to have a pull-up resistor to VTT on these
> lines?
>
> If I don't use them, how is the dynamic current supposed to be supplied
> to the lines?
>
>
>
> What could go wrong (if at all) if I don't include them in the design?
>
>
>
> Thanks
>
>
>
> Itzhak hirshtal
>
>
>
>
>
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