[SI-LIST] Re: The necessity of Pull-up resistors in DDR2
- From: Hany Fahmy <hfahmy@xxxxxxxxxx>
- To: "'ihirshtal@xxxxxxxxxx'" <ihirshtal@xxxxxxxxxx>, "'hermann.ruckerbauer@xxxxxxxxxxxxx'" <hermann.ruckerbauer@xxxxxxxxxxxxx>, "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Sun, 31 Jan 2010 06:11:55 -0800
They call such termination to VTT as CTT: or center-tab-termination to imply
that the termination is connected to a mid-level between VDD and GND for MA/CMD
bus.
Agree with Hermann that if the Signal-integrity looks good (may be short
routing of the bus and good impedance matching with no
return-path-discontinuity), then it may not need such termination.
CTT does also help reduce di/dt for the data-bus as the dynamic-current is
smaller and therefore smaller sso noise. I guess that u will still use ODT for
the data-bus. The Q here is mainly about the MA/CMD bus.
Agree with Hermann also that special attention to the OS and US for
non-terminated bus: not only looking at the peak OS voltage but also looking at
the area V.ns of the peak as it does impact the reliability of the device.
Hany Fahmy (Nvidia Corporation)
----- Original Message -----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx>
To: hermann.ruckerbauer@xxxxxxxxxxxxx <hermann.ruckerbauer@xxxxxxxxxxxxx>;
si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
Sent: Sun Jan 31 05:43:18 2010
Subject: [SI-LIST] Re: The necessity of Pull-up resistors in DDR2
Hello Hermann
My use of VTT stems from the SSTL18 protocol, where 1 of the termination
options there is connecting RT to VTT (see Fig. 3 in JESD8-15a) at the receiver
end of the line.
You're right about the dynamic and DC current - I've confused them.
Don't you think there might be a problem when the bus is floating? See Bill
Grenoble's response
Thanks
Itzhak Hirhtal
________________________________
From: Hermann Ruckerbauer [mailto:hermann.ruckerbauer@xxxxxxxxxxxxx]
Sent: Sunday, January 31, 2010 3:31 PM
To: si-list@xxxxxxxxxxxxx; Hirshtal Itzhak
Subject: Re: [SI-LIST] The necessity of Pull-up resistors in DDR2
Hello Itzhak,
not sure if I use pull up in the same way you do ..
The definition I know is that a "Pull up" would terminate to VDDQ (and a "Pull
down" terminate to VSSQ).
It seems that you terminate to VTT what does not have a real name in my wording
:-) (maybe "pull mid" ?)
Of course you can run a DDR2 CA bus without termination.
If the SI Simulation is shwoing a result that fulfills alls input parameters of
the DRAM (Setup/Hold, slew rates, ringbacks, ..) there is no reason to use a
termination.
You need to take a close look to overshoots (and undershoots), as this one of
the most critical things when using a rail to rail signaling with no
termination.
When this lines are terminated e. g. the high level is not reaching VDDQ and
therefor even an overshoot over the high level is not a problem. If there is no
termination the high level = VDDQ and therefore an overshoot can cause trouble.
But basically this is part of the comment "if the SI simulations result
fulfills input parameter requirement"
but I do not understand the comment on dynamic current. The situation is quite
similar that the dynamic current need to load the capacitances on the bus. The
difference is the DC current that is missing in the system without termination.
The improvement in Power and the lower component cost is maybe not the factor
to do such a design, but the big advantage is the real estate on the board that
is gained.
Hermann
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schrieb Hirshtal Itzhak:
Hello SI Experts
I've conducted some pre-layout simulations on a DDR2 bus connected to
on-board DDR2 devices.
I found out that I get proper waveforms even if I don't use pull-up
resistors on the Address & Control lines.
I wonder if this is an acceptable result! I've always been using those
pull-up resistors in previous designs.
Is it a mandatory requirement to have a pull-up resistor to VTT on these
lines?
If I don't use them, how is the dynamic current supposed to be supplied
to the lines?
What could go wrong (if at all) if I don't include them in the design?
Thanks
Itzhak hirshtal
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