[SI-LIST] Re: TDR and S-parameter
- From: "Antonis Orphanou" <orphanou@xxxxxxxxxxxx>
- To: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- Date: Tue, 1 Oct 2013 20:52:57 +0000
cool Scott, Jory
I agree with your statements. Loss in the TDR relationship is accounted for
only in the characteristic impedance but not the return wave attenuation. I
guess this is where the TDR definition is not sufficient in accounting for all
the losses in the interconnect as far as the reflected wave is concerned. The
received waveform is blind to what happens beyond the input. Yeah sometimes
gating your waveforms can help improve the TDR a little bit...
Regards
Antonis.
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
Sent: Tuesday, October 01, 2013 11:35 AM
To: Antonis Orphanou
Cc: weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: TDR and S-parameter
Antonis
if we are trying to measure an unknown in the middle of a line, it's reflected
impedance is dependent upon what occurs before it on the line. My point is
that you cannot disregard what happens between the probe and the thing that you
are trying to measure.
As an example, a semiconductor package often has traces with very fine 25
micron lines. Because of launch discontinuities in the measurement apparatus,
whether you are using microprobes, or some sort of connectorized launch with
cables and RF connectors, there is a period of time in the TDR plot where a
measurement is not possible, due to ringing. This also occurs with TDR
measurements made of printed circuit board impedance test strips. As a result,
it makes sense to wait until the ringing has dissipated before taking a TDR
impedance measurement. However, it is important to know that the measurement
made includes accumulated losses, which also must be removed from the final
Impedance measured. There are standards where this is not done, and as a
result, the reported impedance of the trace is higher than reality. This
happens all the time with PCB and Package measurements where narrow traces are
being measured. For semiconductor packages this can represent a 3 to 5 ohm
error.
regards,
Scott
On Tue, Oct 1, 2013 at 2:12 PM, Antonis Orphanou
<orphanou@xxxxxxxxxxxx<mailto:orphanou@xxxxxxxxxxxx>> wrote:
By definition the TDR will solve for the input impedance to the line as a
function of time. This input impedance is a function of the characteristic
impedance and the reflection coefficient. The reflection coefficient (S11) in
time will represent the interconnect deviation of the input impedance relative
to the line or targeted characteristic impedance.
With frequency changes (rise time), the characteristic impedance of the
interconnect and the reflection coefficient will change; hence the input
impedance to the interconnect ( and the TDR) will also change.
I am not sure why we want to distinguish ac impedance and intrinsic impedance
when the TDR definition is just a straight forward dependency on the
characteristic impedance and the reflection coefficient along the interconnect.
Regards
Antonis
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>
[mailto:si-list-bounce@xxxxxxxxxxxxx<mailto:si-list-bounce@xxxxxxxxxxxxx>] On
Behalf Of steve weir
Sent: Tuesday, October 01, 2013 9:26 AM
To: si-list@xxxxxxxxxxxxx<mailto:si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: TDR and S-parameter
Bala, the resistance gets added in both directions: Lossless Tx line Z
+ 2X resistance.
Steve
On 10/1/2013 8:57 AM, bala wrote:
> Scott,
> As per my understanding,At high frequencies due to skin effect my electrons
> are not utilizing my entire cross section and resistance increases.(As
> this is happening at high frequency I will call this as AC resistance).so
> my tdr impedance is my intrinsic impedance+ac resistance.
>
> bala
> On 30 Sep 2013 21:48, "Scott McMorrow"
> <scott@xxxxxxxxxxxxx<mailto:scott@xxxxxxxxxxxxx>> wrote:
>
>> Eric
>> This statement is not totally true:
>>
>> "Given this condition, the characteristic impedance read from the flat
>> region of the reflected signal will be independent of the rise time. It is
>> intrinsic to the interconnect."
>>
>> The characteristic impedance read from the flat region of the reflected
>> signal is independent of the rise time, and is the sum of the intrinsic
>> impedance of the flat region of the interconnect ... *plus ...* the
>> accumulated round trip DC resistance of the interconnect.
>>
>> This is is an important distinction. Unless accumulated interconnect
>> resistance is removed from a TDR measurement, a TDR measurement always
>> indicates an impedance that is higher than the actual intrinsic impedance
>> of an interconnect section. This accumulated resistance represents an
>> error in impedance measurements, and is often disregarded. It becomes a
>> significant error when TDR-ing structures which are fed by narrow traces.
>> We experience this issue all the time when correlating measurements of
>> semiconductor packages with modeling.
>>
>>
>> best regards,
>>
>> Scott
>>
>>
>>
>> On Mon, Sep 30, 2013 at 11:59 AM, Eric Bogatin
>> <eric@xxxxxxxxxxxxxxx<mailto:eric@xxxxxxxxxxxxxxx>>
>> wrote:
>>
>>> Bala-
>>>
>>>
>>> Do not confuse characteristic impedance with "impedance" when displayed
>> in
>>> a
>>> TDR type measurement or simulation.
>>>
>>>
>>>
>>> The characteristic impedance of an interconnect only applies, by
>>> definition,
>>> to a uniform transmission line. If it is not uniform, it has no
>>> "characteristic" impedance. All you can do is sort of approximation the
>>> interconnect as a uniform transmission line and then estimate the
>>> approximate characteristic impedance.
>>>
>>>
>>>
>>> However, every interconnect will reflect some signal from a 50 Ohm source
>>> due to its "instantaneous" impedance encountered by the step edge.
>>>
>>>
>>>
>>> The amount of reflected signal depends on the rise time of the signal,
>> the
>>> impedance profile and the electrical length of the interconnect.
>>>
>>>
>>>
>>> If you have a uniform transmission line, and the rise time of your step
>>> edge
>>> is short compared to its time delay, you will see a flat top or flat
>>> bottom.
>>> From this reflected value, you can read off the front screen the
>>> characteristic impedance. Given this condition, the characteristic
>>> impedance
>>> read from the flat region of the reflected signal will be independent of
>>> the
>>> rise time. It is intrinsic to the interconnect.
>>>
>>>
>>>
>>> However, even if you have a uniform transmission line, but your TDR step
>>> edge is electrically long, the value of the reflected signal, and the
>>> extracted "impedance" will depend on the rise time of the edge. It is not
>>> intrinsic to the interconnect.
>>>
>>>
>>>
>>> When comparing the TDR response for different models, be sure to use the
>>> same rise times, and edge profiles. Unless there is a flat top or bottom,
>>> what you are comparing is the instantaneous impedance at a given rise
>> time,
>>> which is only a limit on the characteristic impedance.
>>>
>>>
>>>
>>> I cover this topic in my book, Signal and Power Integrity- Simplified
>>>
>>>
>>>
>>> --eric
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> *******************************************************
>>> Dr. Eric Bogatin, Signal Integrity Evangelist
>>>
>>> Bogatin Enterprises
>>>
>>> Setting the Standard for Signal Integrity Training
>>> web site: <http://www.bethesignal.com/>
>>> www.beTheSignal.com<http://www.beTheSignal.com>
>>>
>>> Blog: <http://www.bethesignal.com/blog>
>>> www.beTheSignal.com/blog<http://www.beTheSignal.com/blog>
>>>
>>> Twitter @beTheSignal
>>> e: <mailto:eric@xxxxxxxxxxxxxxx<mailto:eric@xxxxxxxxxxxxxxx>>
>>> eric@xxxxxxxxxxxxxxx<mailto:eric@xxxxxxxxxxxxxxx>
>>>
>>> Laboratory: Connected Community Networks
>>>
>>> 105 S Sunset St, Suite J
>>>
>>> Longmont, CO 80501 USA
>>>
>>> cell: 913-424-4333 skype: eric.bogatin
>>> ***********************************************
>>>
>>>
>>>
>>>
>>>
>>> Msg: #1 in digest
>>>
>>> Date: Sun, 29 Sep 2013 23:49:39 +0530
>>>
>>> Subject: [SI-LIST] TDR and S-parameter
>>>
>>> From: bala <balaseven@xxxxxxxxx<mailto:balaseven@xxxxxxxxx>>
>>>
>>>
>>>
>>> Hi Experts,
>>>
>>> I am validating one high speed interface for my new design.I just wanted
>> to
>>> ensure differential impedance of my IC package+PCB interconnect+backplane
>>> connectors are in 90-110 ohm range.
>>>
>>> My connector vendor shared their s-parameter model and their TDR
>>> report.Their plot shows 85-102 ohm variation.They just applied 100 ps
>>> square
>>> pulse and generated their TDR plot, whereas in my tool i generated TDR
>>> directly from S-parameter(no pulse applied,this tool has this option),and
>>> my
>>> plot shows different result(95-103 ohm).I am just checking with my
>> vendors
>>> on this.My question is,no vendor always share their report along with
>> their
>>> model.Many of us would have decided their channel's TDR is good as it
>> shows
>>> 95-103.But actually different tool has different method to generate TDR
>> and
>>> shows different plot,like my vendors' report and my report.So if someone
>>> provide their model without their own correlation report,how do we
>> believe
>>> our results are correct?
>>>
>>> --
>>>
>>> bala
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> ------------------------------
>>>
>>>
>>>
>>> Msg: #2 in digest
>>>
>>> Subject: [SI-LIST] Re: TDR and S-parameter
>>>
>>> From: "Alfred P. Neves" <al@xxxxxxxxxxxxxxxxx<mailto:al@xxxxxxxxxxxxxxxxx>>
>>>
>>> Date: Sun, 29 Sep 2013 11:31:06 -0700
>>>
>>>
>>>
>>>
>>>
>>> I would correspond the two TDR (one from S-parameters, the other directly
>>> measured) with a standard like stepped impedance Beatty standard, along
>>> with
>>> a 50ohm airline.
>>>
>>>
>>>
>>> Anritsu and Maury market them as calibration validation standards. They
>>> are a little tricky to use because they need to be connected with a bit
>> of
>>> care, since there is either only one or no beads supporting the airline.
>>>
>>>
>>>
>>> Our website has a DesignCon tutorial we did with Anritsu last year that
>>> discusses this measurement validation approach. " Methods of Improving
>> 3D
>>> EM Model Development and Associated Time/Frequency Domain Measurements",
>> we
>>> wrote it with Jon Martens, Bob Buxton at Anritusu and Josiah Bartlett at
>>> Tektronix.
>>>
>>>
>>>
>>>
>>>
>>> Both coaxial and planar standards (Channel Modeling Platforms) IMHO are
>> the
>>> most underutilized tools for the SI engineers. Coaxial have specific
>>> strengths for measurement validation (they are NIST traceable), versus
>>> planar standards (channel modeling platforms) have ability to also
>> include
>>> correspondence of measurement and 3D EM solver analysis.
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> Products for the Signal Integrity Practitioner
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> Alfred P. Neves
>>>
>>> Chief Technologist
>>>
>>>
>>>
>>>
>>>
>>> Office: 503-679-2429
>>>
>>>
>>>
>>> www.wildrivertech.com<http://www.wildrivertech.com>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
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>>
>> --
>>
>> Scott McMorrow
>> Teraspeed Consulting Group LLC
>> 16 Stormy Brook Rd
>> Falmouth, ME 04105
>>
>> (401) 284-1827 Business
>>
>> http://www.teraspeed.com
>>
>> Teraspeed(r) is the registered service mark of
>> Teraspeed Consulting Group LLC
>>
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