[SI-LIST] Re: Splitting the power plane

  • From: Jory McKinley <jory_mckinley@xxxxxxxxx>
  • To: Ravinder.Ajmani@xxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Sat, 13 Nov 2010 11:29:56 -0800 (PST)

Hello Ravinder,
It all depends on the required performance targets for each IO or collectively 
as a whole at the Asic chip.  First you will need to understand the amount of 
switching current and edge rate that could be present in the package and 
determine if you can live with one uniform plane with all the IO switching or 
you may need to have multiple planes if noise levels cannot be met.  Second 
there is the issue of isolation of board noise (lower frequency) making into 
the 
package and disrupting sensitive circuits.  Typically you can get better 
isolation with separate planes but this is a trade off with increased board 
complexity.  
Generate Z11 and S21 curves from DC to daylight at the chips IO for both cases 
(some assembly required, decoupling optimization and on-chip caps) and the 
numbers should point you in the right direction.
Regards,
-Jory



________________________________
From: "Ravinder.Ajmani@xxxxxxxxxxxxxx" <Ravinder.Ajmani@xxxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Fri, November 12, 2010 5:48:25 PM
Subject: [SI-LIST] Splitting the power plane

Hi Experts,
Our ASIC vendor advises splitting the power plane between DDR I/Os and 
other I/Os using a ferrite bead and bulk capacitance.  I prefer not to 
slice the power plane unless it is between Analog and Digital sections of 
the chip.  I will appreciate suggestions from you on this subject.

Thanks.

Regards, 
Ravinder Ajmani
Server PCB Development
Hitachi Global Storage Technologies


Email: Ravinder.Ajmani@xxxxxxxxxxxxxx

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