[SI-LIST] Re: Splitting the power plane

  • From: Dan Smith <Dan.Smith@xxxxxxxxx>
  • To: "Ravinder.Ajmani@xxxxxxxxxxxxxx" <Ravinder.Ajmani@xxxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 12 Nov 2010 17:02:14 -0800

Ravinder,

Ask you ASIC vendor to provide you with a VCC ripple requirement over a certain 
frequency band for all voltage rails.  Then, use that to design a power 
distribution system (PDS) that meets those requirements (e.g., loop 
compensation in your power supply design, decoupling capacitors, etc.).  This 
has been an uphill battle with vendors but is finally gaining some traction.  
If you get resistance from them (and you probably will) provide them with the 
following for discussion:

X = Y*Z where
X = output
Y = filter
Z = input

Vendors are happy to always tell you what the filter should be (e.g., Y in the 
above equation) with no regard to what Z is (ripple from your PDS).  Thus, 
there is no way they can guarantee what X will be even if one uses their 
recommended filter Y.  Good engineering begins with requirements (what does the 
ripple at the power pins need to be to guarantee performance) not application 
notes.

Good Luck

Dan

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Ravinder.Ajmani@xxxxxxxxxxxxxx
Sent: Friday, November 12, 2010 2:48 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Splitting the power plane

Hi Experts,
Our ASIC vendor advises splitting the power plane between DDR I/Os and
other I/Os using a ferrite bead and bulk capacitance.  I prefer not to
slice the power plane unless it is between Analog and Digital sections of
the chip.  I will appreciate suggestions from you on this subject.

Thanks.

Regards,
Ravinder Ajmani
Server PCB Development
Hitachi Global Storage Technologies


Email: Ravinder.Ajmani@xxxxxxxxxxxxxx

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