[SI-LIST] Re: Splitting the power plane
- From: Cosmin Iorga <ci249534@xxxxxxxxx>
- To: Ravinder.Ajmani@xxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 15 Nov 2010 10:59:47 -0800 (PST)
Ravinder,
I think it depends quite significantly on your specific design and spectral
distribution of self-generated and incoming supply noise. The ferrite bead
will
provide isolation for a finite frequency range with the expense of weakening
the
power distribution for DDR I/Os (split planes result in higher inductance and
placement limitations for decoupling capacitors). So the other I/Os and
circuits will benefit, but most probably the DDR self-generated noise will be
worse. Now since there are additional PDN coupling paths/mechanisms on the
package and chip, you may want to evaluate/simulate the actual injected noise
in
the other supplies to make a decision.
Cosmin Iorga,
NoiseCoupling.com
http://www.noisecoupling.com
tel: (805)231-9786
________________________________
From: "Ravinder.Ajmani@xxxxxxxxxxxxxx" <Ravinder.Ajmani@xxxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Fri, November 12, 2010 2:48:25 PM
Subject: [SI-LIST] Splitting the power plane
Hi Experts,
Our ASIC vendor advises splitting the power plane between DDR I/Os and
other I/Os using a ferrite bead and bulk capacitance. I prefer not to
slice the power plane unless it is between Analog and Digital sections of
the chip. I will appreciate suggestions from you on this subject.
Thanks.
Regards,
Ravinder Ajmani
Server PCB Development
Hitachi Global Storage Technologies
Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
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