[SI-LIST] Splitting the power plane

  • From: Ravinder.Ajmani@xxxxxxxxxxxxxx
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 12 Nov 2010 14:48:25 -0800

Hi Experts,
Our ASIC vendor advises splitting the power plane between DDR I/Os and 
other I/Os using a ferrite bead and bulk capacitance.  I prefer not to 
slice the power plane unless it is between Analog and Digital sections of 
the chip.  I will appreciate suggestions from you on this subject.

Thanks.

Regards, 
Ravinder Ajmani
Server PCB Development
Hitachi Global Storage Technologies


Email: Ravinder.Ajmani@xxxxxxxxxxxxxx

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