[SI-LIST] Re: Sj frequency and relation to BER
- From: Iliya Zamek <i_zamek@xxxxxxxxx>
- To: "al@xxxxxxxxxxxxxxxxx" <al@xxxxxxxxxxxxxxxxx>, "istvan.novak@xxxxxxxxxxx" <istvan.novak@xxxxxxxxxxx>, "ah.vinod@xxxxxxxxx" <ah.vinod@xxxxxxxxx>, SI-LIST <si-list@xxxxxxxxxxxxx>
- Date: Mon, 17 Jun 2013 10:14:14 -0700 (PDT)
Vinod,
We observed Jitter resonance at 36MHz testing system of Chip/Package/PCB. These
Jitter peaking happen due to resonance of a
corresponding PDN system. You might want to take a look on measurement results
of Clock Tree jitter presented on Figure 3 in
http://www.semtech.com/power-management/On-Chip-Jitter-and-System-Power-Integrity.pdf
I/O experence similar resonances (see
http://application-notes.digchip.com/038/38-21381.pdf).
While it is not enough data to say that this is a reason in your case, it has
high probability that it is the same effect that we studied.
Best regards,
Iliya Zamek
________________________________
From: Alfred P. Neves <al@xxxxxxxxxxxxxxxxx>
To: "istvan.novak@xxxxxxxxxxx" <istvan.novak@xxxxxxxxxxx>; "ah.vinod@xxxxxxxxx"
<ah.vinod@xxxxxxxxx>; SI-LIST <si-list@xxxxxxxxxxxxx>
Sent: Monday, June 17, 2013 8:40 AM
Subject: [SI-LIST] Re: Sj frequency and relation to BER
Run clock data and examine the output with a spectrum analyzer, or examine CDR
directly with SA with data in. You probably don't have enough loop gain for
33MHZ SJ, or excessive peaking in the CDR loop response.
Transition density impacts gain and pll stability, so don't ignore pattern
sensitivity.
Sent to you confidentially by ipad2.
On Jun 17, 2013, at 6:05 AM, Istvan Novak <istvan.novak@xxxxxxxxxxx> wrote:
> Vinod,
>
> I just pointed out that the 200ps bit time and the 40ps jitter deviation
> are in integer relationship...
>
> Unless you see the failure still at 33MHz with detuned deviation or bit
> rate, I would not be fully convinced that the trouble frequency is in
> fact 33MHz, it could be just a coincidence.
>
> If it consistently fails at 33MHz with detuned deviation as well, the
> reason might be something to do with how the CDR works, and unless you
> know those details, it may be hard to speculate. Could be that you hit
> the natural frequency of the PLL or you hit the reference frequency of
> the PLL or one of its harmonics.
>
> Regards,
>
> Istvan Novak
> Oracle
>
> On 6/17/2013 8:04 AM, vinod ah wrote:
>> hi,
>>
>> Can you please help me out to understand the relation between bit time
>> of 200ps and 33MHz Sj. I understand that 40ps of Sj is integer
>> multiple of 200ps bit time, but what i observe is even with 40ps Sj
>> @10MHz or 40ps Sj @50MHz, no BER issue.
>>
>> BER fails only for 40ps Sj @33MHz.
>>
>> Regards
>> Vinod A H
>>
>> On Mon, Jun 17, 2013 at 5:27 PM, Istvan Novak <istvan.novak@xxxxxxxxxxx>
>> wrote:
>>> Vinod,
>>>
>>> Your nominal bit time and deviation of sinusoid jitter is in perfect integer
>>> relationship, which could make it statistically very sensitive to small
>>> variations of parameters.
>>> I just wonder how your circuit would behave if you detuned one or the other
>>> slightly but noticeably.
>>>
>>> Regards,
>>>
>>> Istvan Novak
>>> Oracle
>>>
>>>
>>>
>>>
>>>
>>> On 6/17/2013 5:31 AM, vinod ah wrote:
>>>> Hi all,
>>>>
>>>> I am testing a serial IO Rx running at 5Gbps to meet BER of 1 in
>>>> 10^-12. I am using BERT for testing where i sweep the Sinusoidal
>>>> jitter (Sj) from 10 MHz to 50 MHz with Sj amplitude being constant
>>>> 40ps.
>>>>
>>>> I see BER failure at 33MHz, while there is no BER failures at any
>>>> other Sj frequencies. The CDR in Rx is having JTF of 3.5MHz, hence it
>>>> won't track the jitter of 10MHz to 50MHz.
>>>>
>>>> So was trying to find what might be causing the BER failure at 33MHz,
>>>> while the BER passes at 50MHz or 10MHz. Unable to understand relation
>>>> of Sj frequency to BER.
>>>>
>>>> Regards
>>>> Vinod A H
>
>
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