[SI-LIST] Signal Integrity - Technical Leader job opening in Cisco, San Jose, CA
- From: "Amit Agrawal (amiagra2)" <amiagra2@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 12 Mar 2012 16:30:37 -0700
We are looking for a signal integrity technical leader in the Signal
Integrity and Power Integrity Group in Unified Access Business Unit
(UABU), Cisco, San Jose. The position (requisition # R918159) is located
in San Jose, CA. The description is given below. If you are interested,
please send your resume or contact me directly.
Best Regards,
Amit P. Agrawal, Ph.D.
Senior Manager, Hardware Engineering
Signal Integrity and Power Integrity
Unified Access Business Unit
Cisco, San Jose, CA
amiagra2@xxxxxxxxx
<http://us.mc834.mail.yahoo.com/mc/compose?to=amiagra2@xxxxxxxxx>
(408) 424-2732 (Office)
Signal Integrity - Technical Leader
(Cisco, San Jose, CA, Req # R918159 )
An experienced signal integrity engineer is being sought for design and
analysis of high speed interfaces and power distribution network. The
successful candidate will be part of signal integrity and Power
Integrity team and will participate in the definition of chip, package,
printed circuit board (PCB), and system interconnects. Within a
concurrent engineering environment, the individual will be part of a
larger team with system architects, logic designers, ASIC engineers, and
SI engineers in creation of next generation networking products.
This group works on present and next-generation cost-sensitive yet high
performance and high volume products.
Your responsibilities will include but not be limited to:
- Working experience in high speed serial I/O applications, PLLs,
transceiver/SERDES operations
- Definition of signaling and package technology for high performance
ASICs
- Simulating and/or analyzing and/or generating power delivery network
requirements
- Understanding signal integrity and timing in order to budget and
evaluate trade-offs between design parameters to determine a solution
space that is high volume manufacturable
- Generating the routing requirements and electrical margins for
specific interfaces and verifying their correctness
Typically requires BSEE/MSEE/Ph.D combined with 5-7+ years of related
experience, Proficiency with spice (or equivalent) circuit simulation,
field-solver and time/frequency domain analysis, familiarity with high
speed serdes design, PLL and LVDS, CML and other high-performance I/O
technologies, ASIC design experience with I/O selection and
simulation/validation, solid background on transmission line theory are
necessary. In depth understanding of electromagnetic theory is a plus.
Experience with available CAD tools such as HSPICE, Sisoft, HFSS, FDTD
tools, MoM tools, Sigrity - PowerSI, Sentinel-PI, Siwave, Q3D, Agilent
ADS, Cadence SI tools or related tools is required. Experience
correlating simulation results with lab measurements using
oscilloscopes, TDRs, VNAs, and BERTScope is a plus. Self motivation,
teamwork and strong communication skills are essential.
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