[SI-LIST] Re: SV: Re: Copper Fill --- correction
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: leeritchey@xxxxxxxxxxxxx
- Date: Fri, 14 Jun 2002 09:46:14 -0700
There are several types of "fill areas" used on the outside layers. The
first is the fill of "dots" as Lee calls them on to create a uniform
copper distribution. The second is the use of larger copper fills for
additonal power distribution.
Lee is quite correct about the first type of fill done by PCB
fabricators. As long as the size of the dots is small, and they remain
unconnected to each other, there is no SI, resonance or EMI issue. If
traces are routed underneath this type of fill, the trace will see a
reduction in characteristic impedance.
For the second type commonly used for power and ground fill, there can
be issues of resonance at high frequencies and potential EMI problems.
These fill areas are often used for additional power distribution for
specific devices, or for additional interplane capacitance.
For the record, any large planar surface has the potential to resonate,
whether it be a power and ground plane pair or some top layer area fill.
Care should be taken in the engineering of these structures when
dealing with high-frequency signals in the system. I have one case
where a high-frequency stripline layer with blind vias was created on
layer 2 by placing a ground fill area over the top on layer 1. Layer 3
was also a full ground plane. The two planes were connected by stitch
vias along the periphery of the area. Each via in the fence was placed
250 mils apart. Short differential stripline and single ended stripline
test traces were placed in this area. For the differential stripline,
there was no reduction in performance, since there was little or no
common mode energy being injected into the planes. However, with single
ended stripline, a VNA sweep showed a resonance point in the 3 GHz
region. This resonance was caused by the cavity formed by the stitch
vias along one of the dimensions. Addition of vias at the center of the
cavity pushed the resonance point up to twice that frequency.
Regards,
Scott
Ritchey Lee wrote:
>This "fill" on outer layers by PCB fabricators is done to create a
>uniform distribution of copper for purposes of achieving plating
>uniformity. It has no other role than this. It is nearly always a
>pattern of dots that are not connected to anything in the finished PCB.
>These do not cause EMI problems.
>
>It troubles me to see all of the speculation being done on this topic
>without any analysis to go with it. That's how useless rules of thumb
>get started.
>
>It would be wise to adopt part of the physicans' crede which states "
>first, do no harm". In this context it means making sure that the rules
>of thumb that are offered don't haver an unintended side effect that
>degrades the design. Many of the classsic rules of thumb do just this.
>
>Lee
>
>Mellberg Hans wrote:
>
>
>
>>Usually the PCB vendor will determine if a certain
>>amount of copper fill is required. I have seen some
>>motherboards with little square pads that varried in
>>size to compensate (or "balance") for the copper on
>>the other side of that laminate. The fill was not on
>>the layout. The same design by another PCB vendor did
>>not use copper balance fill. The performace was
>>similar except for some additional EMI from the board
>>with the extra fill.
>>
>>--- Jason D Leung <Jason.d.Leung@xxxxxxxxxxx> wrote:
>>
>>
>>>Hi Anders Ekholm:
>>>thanks
>>>then how do we know when it is necessary for us to
>>>have copper balance, and how much
>>>copper we should be using to do the job
>>>
>>>best Regards
>>>Jason
>>>
>>>
>>>
>>>
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--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
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