[SI-LIST] Re: SV: Re: Copper Fill --- correction
- From: Jeff Jones <JJones@xxxxxxxx>
- To: "'leeritchey@xxxxxxxxxxxxx'" <leeritchey@xxxxxxxxxxxxx>,Jason.d.Leung@xxxxxxxxxxx
- Date: Fri, 14 Jun 2002 11:38:14 -0400
our pcb warping was due to incorrect layer stackups. =20
-----Original Message-----
From: Ritchey Lee [mailto:leeritchey@xxxxxxxxxxxxx]
Sent: Friday, June 14, 2002 11:04 AM
To: Jason.d.Leung@xxxxxxxxxxx
Cc: Anders Ekholm (ERA); scott@xxxxxxxxxxxxx; RayCaliendo@xxxxxxxxxx;
silist
Subject: [SI-LIST] Re: SV: Re: Copper Fill --- correction
No, its' not necessary to do this to achieve copper balance. I've =
designed
hundreds of
multilayer PCBs and witnessed the design of many hundreds more where =
this
technique was
not used and none of them warped.
Lee
Jason D Leung wrote:
> Hi Anders Ekholm:
> thanks
> then how do we know when it is necessary for us to have copper =
balance,
and how much
> copper we should be using to do the job
>
> best Regards
> Jason
>
> "Anders Ekholm (ERA)" wrote:
>
> > Hi.
> > For other reasons than Signal Integrity ones, we want a uniform =
copper
distribution
> > on the PCB, since otherwise it will bend. A uniform copper =
distribution
is good
> > for mechanical reasons.
> >
> > Regards /Anders Ekholm
> >
> > -----Ursprungligt meddelande-----
> > Fr=E5n: Jason D Leung [mailto:Jason.d.Leung@xxxxxxxxxxx]
> > Skickat: den 14 juni 2002 15:00
> > Till: scott@xxxxxxxxxxxxx; RayCaliendo@xxxxxxxxxx
> > Kopia: silist
> > =C4mne: [SI-LIST] Re: Copper Fill --- correction
> >
> > Hi guys,
> > I understand that if the fill is too close to the signal trace it =
is
going
> > to increase the capacitance and decrease the impedance in turn.
> > But my question will be why do we need to put a fill on the pcb. ( =
this
may
> > be a basic question , and I always heard my colleagues saying it, =
but it
> > helps me alot, if there's a kind soul to help me to understand it)
> >
> > thanks in advance
> > Regards
> > Jason
> >
> > Scott McMorrow wrote:
> >
> > > Okay, now I really need some coffee ... and it's 5:30 in the =
evening.
> > > Here's yet another correction and more elaboration.
> > >
> > > A square patch of copper on top of a dielectric and plane forms a
crude
> > > cavity resonator which will have a number of natural resonant
> > > eigenmodes. The first resonant point is a half-wave resonance. =
The
> > > resonance frequency is equal to the round trip of a wave =
propagating
> > > back and forth across the region, much like what would happen in =
a
> > > square pool of water between the two walls. For a one square =
inch
patch
> > > of copper, the resonant frequency on FR-4 is somewhere between =
2.7 and
> > > 3.3 GHz
> > >
> > > A very crude square patch
> > >
> > > w
> > > --------------
> > > | | resonant frequency =3D 1/( 2 * w * =
Vp)
> > > | | Vp =3D velocity of propagation of wave =
in
> > > dielectric medium =3D c/sqrt(Er)
> > > | | w =3D width and height of square
> > > | |
> > > | |
> > > ---------------
> > >
> > > Adding vias to the patch effectively pins the structure down and
raises
> > > it's resonant frequency. The spacing of the vias control the
resonance,
> > > with a half-wave resonance being the lowest generally supported =
by the
> > > structure. Stitching the patch at all four corners actually does
nothing
> > > to change the resonant frequency of the cavity. However, placing =
a
> > > fifth via at the center will push the resonance up by a factor of =
2.
> > >
> > > w
> > > @------------@
> > > | | resonant frequency =3D 1/( 4 * w * =
Vp)
> > > | | Vp =3D velocity of propagation of =
wave in
> > > dielectric medium
> > > | @ | w =3D width and height of square
> > > | | @ =3D Via stitch
> > > | |
> > > @------------@
> > >
> > > In essence, the via spacing has changed from w to w/2. These =
formulas
> > > are quite approximate, but will place us in the general playing =
field.
A
> > > full-wave field solver such as PowerSI from Sigrity, or SIwave =
and
HFSS
> > > from Ansoft, will provide much more exact resonance frequency
analysis.
> > >
> > > So, the "rough" formula I gave for via spacing should be:
> > >
> > > via spacing =3D1/(2 * (f * Vp)) not 2/(f * Vp) as I had =
indicated.
> > >
> > > In my previous example, this would amount to a via spacing of =
0.59
> > > inches, not 1.18.
> > >
> > > Sorry about my confusion.
> > >
> > > Scott
> > >
> > > --
> > > Scott McMorrow
> > > Teraspeed Consulting Group LLC
> > > 2926 SE Yamhill St.
> > > Portland, OR 97214
> > > (503) 239-5536
> > > http://www.teraspeed.com
> > >
> > > Scott McMorrow wrote:
> > >
> > > > My equation below has an error.
> > > >
> > > > The maximum via spacing should be:
> > > >
> > > > 2/(f * Vp)
> > > >
> > > > This accounts for the half-wave resonance which occurs between =
vias.
> > > >
> > > >
> > > > regards,
> > > >
> > > > Scott
> > > >
> > > >
> > > > Scott McMorrow wrote:
> > > >
> > > >> Ray,
> > > >>
> > > >> When the separation of the copper fill from any signal is > 20
times
> > > >> the signal-to-plane spacing there is no effect on the signals. =
So,
> > > >> for 5 mil dielectric thickness, the fill area to signal trace
> > > >> clearance should be 100 mils or greater. I would also suggest
> > > >> grounding each fill area at multiple points to eliminate =
possible
EMI
> > > >> coupling problems.. At a minimum, use ground stitch vias at =
four
> > > >> corners to contain resonances of the fill area. For extremely =
high
> > > >> speed multi-gigahertz systems, the vias should be spaced a =
maximum
> > > >> distance apart of 1/(f * Vp) apart. Where f =3D the upper =
frequency
of
> > > >> operation and Vp is the velocity of propagation of signals =
within
the
> > > >> dielectric.
> > > >>
> > > >> For FR4 Vp is around 180ps/in. For 3.125 Gbps signallling the
upper
> > > >> frequency you are concerned with is the 3rd harmonic of the
switching
> > > >> frequency, 4.68 GHz. In this case, the maximum stitch via =
spacing
> > > >> would be
> > > >> 1/(4.68e9 * 180e-12) =3D 1.18 inches.
> > > >>
> > > >> Best regards,
> > > >>
> > > >> Scott
> > > >>
> > > >>
> > > >>
> > > >>
> > > >
> > >
> > > =
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