[SI-LIST] Re: SSO and load capacitance
- From: Larry Smith <LSMITH@xxxxxxxxxx>
- To: steve weir <weirsi@xxxxxxxxxx>
- Date: Wed, 3 Aug 2011 09:20:32 -0700
Steve, Scott - I am not sure of precise definitions but I have always used SSN
and SSO (noise and outputs) interchangeably. SSN has become a diluted down
'catch all' word that is applied to all imaginable noise. I've run into people
that call core logic noise "SSN." This is unfortunate because we lose the
language we need to discuss single ended output drivers whose current return
paths are on the power and ground structures.
I still think it is a good idea to confine SSN and SSO to the noise waveforms
launched into a victim transmission line from simultaneously switching single
ended IO drivers. The SSN energy is generated mostly by inductive coupling in
the "vertical structures" including the package vias, package balls and the PCB
vias. These are often stacked right on top of each other and the mutual
inductance comes "per unit length." The PCB vias are often the longest
vertical structure (if current goes all the way to transmission lines on the
bottom of the board) and therefore often contribute most of the offending
mutual inductance. So this is not just a die/package problem because the board
contributes up to 3x the energy launched into a victim transmission line
compared to the package. The package ball definition determines the PCB via
pattern so (in my opinion) the component houses have to take responsibility for
the SSN generated in the board all the way past the "break out" region for
board traces.
To Scotts point, there is certainly a system level analysis to be done that
includes the characteristics of the offending silicon as well as the rest of
the system (package, PCB, traces, load, etc). But this is the system response
to the SSN generated near the driver. The component houses are obligated to
provide a product that that only launches a "tolerable" amount of SSN noise
into the system. That means a proper number of return paths in geometrical
patterns that are effective in reducing the mutual inductance (i.e. 8:1:1
signal:power:ground ratio where every signal is reasonably close to a return
path). The component houses must do this analysis for a reasonable PCB via
depth to break out all the signals. After that, it is up to the system houses
to insure that nets are properly loaded and terminated in a way that gives a
high probability of good signal integrity.
Going back to the original question on this thread, load capacitance at the far
end of transmission line has no effect on the amount of SSN energy launched
into a victim net from aggressor nets. The height of the SSN glitch seen at
the victim receiver is actually reduced with more load capacitance. There are
however system reflection issues that are generated by this load capacitance
(non-perfect termination).
Regards,
Larry Smith
-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]
Sent: Tuesday, August 02, 2011 2:12 PM
To: Larry Smith
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: SSO and load capacitance
Normally, when talking about SSN, I confine SSN to refer to disturbance
at the transmit end. Inside the package that consists of PDN common
impedance, and cross-talk. Outside the package the PDN s/b quiet wrt
switching edges, and in my vocabulary line to line coupling there is all
cross-talk.
For transmission lines that are short compared to the bit interval, I
agree that load capacitance can R-C filter some of the induced line to
line noise without bad side effects. In that case the reflections
caused by a capacitive discontinuity will have a chance to die out
before the next transition starts. For transmission lines that are long
enough to hold more than one bit, it gets more complicated. Any memory
of past transitions rattling up and down the channel is usually a bad
thing. A clean source termination will remove most of the reflected
energy from a dirty load termination before it can do harm. If the
source does not match the line, then a fair amount of the junk reflected
off the dirty load is going to become unwanted ISI. I see Scott has
addressed several scenarios where this has caused real design headaches.
I would be cautious of any silicon where the vendor is looking to quiet
down glitches that their suboptimal silicon/package combination induces
with make shift filter networks. In some cases it's a trick that works,
in others it is trading one problem for others.
Best Regards,
Steve.
On 8/2/2011 8:18 AM, Larry Smith wrote:
> Jason - the comment is correct: the worst case SSN waveforms will be found
> with minimum load capacitance. But some explanation is required.
>
> First, SSN can be broken down into two components: inductive coupling and
> PDN. Steve is referring to the PDN part in his response. But usually the
> greatest SSN noise amplitude measured at the far end of a signal transmission
> line comes from inductive coupling, not PDN.
>
> Inductive coupling is related to mutual inductance between aggressor signals
> and the victim signal. It only happens during the rise (fall) time of the
> driver because that is when the di/dt takes place. To a first approximation,
> the voltage noise that gets launched into a victim transmission line (under
> the BGA that makes the SSN) is proportional to m*di/dt where m is the sum of
> the mutual inductance from all the aggressors to the victim and i is the
> current in the aggressors. Mutual inductance occurs in the wire bonds,
> package vias, balls and PCB vias and to a first approximation is proportional
> to the length of these structures.
>
> These days, the aggressor rise time is on the order of 200pSec, which is the
> time that it takes signals to travel about an inch down a transmission line.
> The capacitance load in question is down at the far end of the transmission
> line, let's assume 6 inches. The 200pSec rise time aggressors launch an SSN
> noise pulse into the victim signal net that is approximately 200pSec wide and
> it arrives at the capacitance load about 1000pSec later. The load
> capacitance at the far end will have no effect on the SSN event that launches
> the SSN glitch into the victim transmission line.
>
> When the SSN glitch arrives at the far end of the transmission line, it often
> finds a 50 ohm termination. The noise measured at the far end is identical
> to the glitch launched into the near end, assuming lossless lines. Now if
> there is any capacitance load at the far end, glitch energy goes into
> charging up the load. The measured SSN glitch voltage amplitude will be less
> with more load capacitance.
>
> Regards,
> Larry Smith
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of steve weir
> Sent: Tuesday, August 02, 2011 4:41 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: SSO and load capacitance
>
> Oops the second formula was energy not charge. It should have read
> Qload comes from Qbypass = Vdroop*Cbypass.
>
> Steve
> On 8/2/2011 4:24 AM, steve weir wrote:
>> Jason, there are two possible sources of confusion. The first is
>> possible confusion between output load capacitance with die capacitance
>> per output driver. Your intuition is correct: If we simplify the PDN /
>> driver network to a switched capacitor representation, then we deposit
>> Qload = Vdd*Cload on each output line that switches from low to high,
>> and remove Qload from each output that switches from high to low. For
>> the low to high switching outputs: Qload comes from Qbypass = (Vdd -
>> Vdroop)^2/2*Cbypass.
>>
>> The second source of confusion comes from the fact that any loads that
>> remain statically high can draw current from any load capacitance that
>> connects to the driver outputs, supporting other outputs that switch
>> from low to high.
>>
>> Steve.
>>
>>
>> On 8/2/2011 3:01 AM, Jason Young wrote:
>>> Dear Experts,
>>> I have read a couple of documents are from silicon IP vendors discussing
>>> the number of power/ground pads needed to meet SSO requirements for a given
>>> number of output drivers. These documents mention that worse case
>>> conditions for SSO are with the smallest output load capacitance. At first
>>> this seems counter intuitive. My initial reasoning would be that a larger
>>> capacitance would present a lower impedance load and hence greater dI/dt,
>>> greater IR drop and greater supply rail bounce. Could you please help me
>>> understand?
>>> Regards,
>>> Jason
>>>
>>>
>>>
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>
> --
> Steve Weir
> IPBLOX, LLC
> 150 N. Center St. #211
> Reno, NV 89501
> www.ipblox.com
>
> (775) 299-4236 Business
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
Confidentiality Notice.
This message may contain information that is confidential or otherwise
protected from disclosure. If you are not the intended recipient, you are
hereby notified that any use, disclosure, dissemination, distribution, or
copying of this message, or any attachments, is strictly prohibited. If you
have received this message in error, please advise the sender by reply e-mail,
and delete the message and any attachments. Thank you.
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