[SI-LIST] Re: SSO and load capacitance
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 02 Aug 2011 04:24:18 -0700
Jason, there are two possible sources of confusion. The first is
possible confusion between output load capacitance with die capacitance
per output driver. Your intuition is correct: If we simplify the PDN /
driver network to a switched capacitor representation, then we deposit
Qload = Vdd*Cload on each output line that switches from low to high,
and remove Qload from each output that switches from high to low. For
the low to high switching outputs: Qload comes from Qbypass = (Vdd -
Vdroop)^2/2*Cbypass.
The second source of confusion comes from the fact that any loads that
remain statically high can draw current from any load capacitance that
connects to the driver outputs, supporting other outputs that switch
from low to high.
Steve.
On 8/2/2011 3:01 AM, Jason Young wrote:
> Dear Experts,
> I have read a couple of documents are from silicon IP vendors discussing the
> number of power/ground pads needed to meet SSO requirements for a given
> number of output drivers. These documents mention that worse case conditions
> for SSO are with the smallest output load capacitance. At first this seems
> counter intuitive. My initial reasoning would be that a larger capacitance
> would present a lower impedance load and hence greater dI/dt, greater IR drop
> and greater supply rail bounce. Could you please help me understand?
> Regards,
> Jason
>
>
>
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Steve Weir
IPBLOX, LLC
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