[SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps
- From: "Sanchez, Louis" <louis.sanchez@xxxxxxxxx>
- To: "'whizplayer@xxxxxxxxx'" <whizplayer@xxxxxxxxx>,ahilton@xxxxxxxxxxxxx, hassan@xxxxxxxx
- Date: Thu, 14 Mar 2002 09:56:09 -0800
Alan........
You mentioned placing a resistor in the network. I must have missed one of
the email responses because I cannot find the thread where it is mentioned.
Can you please repeat your suggestion? Duty factor shifts can be
interesting, and destructive if not handled properly in some applications.
With the right time constant (RC coupling) combined with a pattern of 1's
and 0's, the baseline can actually exhibit a low frequency form of
modulation. This can cause thresholding to occur at the receiver at
different points on the edges of the waveform. The result is jitter. An RC
coupled network is such a simple thing, but improperly used can cause
seemingly unexplained anomalies when processing pulse trains of data.
Lou A. Sanchez
-----Original Message-----
From: Bob Patel [mailto:whizplayer@xxxxxxxxx]
Sent: Thursday, March 14, 2002 9:35 AM
To: ahilton@xxxxxxxxxxxxx; hassan@xxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps
Hi!Alan, You bring up a very good point i.e. in AC
coupling with long strings of 0's & 1's will cause the
DC level to shift and depending upon this shift there
could be crossover at the receiver which could lead to
the receiver being sensitive to BER.
In case of 8B/10B which has good DC balance AC
coupling works well although you ahve to pay close
attention to deterministic jitter.
In case of SONET frame when scrambled the max in a
book is 72 and this has to be taken into account.
Bob
--- Alan Hilton-Nickel <ahilton@xxxxxxxxxxxxx> wrote:
>
> Hassan,
>
> I wondered if that might be the thing to do. It's
> also possible in simulation
> (and indeed, frequent practice), to add the resistor
> I suggested to set a DC
> level. In simulation it would be a very large value,
> such as 1 to 10Meg. It
> should do the trick in at most a couple of cycles.
> This is another way of
> implementing Kumar's suggestion of setting the
> initial charge condition on the
> cap.
>
> Also note that this effect is not necessarily a
> "simulation thing" - there is
> some relationship to reality. If you have a cyclical
> signal, like a clock, you
> should indeed get a 0 V DC level. But if it is data,
> a long string of "1"s or
> "0"s will shift the DC level up or down. Even with a
> clock, a duty cycle that is
> not exactly 50% can have a small offset. Try a 45%
> duty cycle in your simulation
> and you'll see what I mean!
>
> Alan Hilton-Nickel
> Transmeta Corp.
>
> Hassan Ali wrote:
> >
> > Thanks all for your suggestions.
> >
> > Actually, the sure way is that suggested by Lou -
> to run the simulation to death!
> > Actually, in my case I had to run it for 2500
> cycles!
> >
> > Kumar's trick is interesting. I tried it but it
> didn't really solve the problem. I still
> > had to run the simulation for a long time to
> obtain 0V DC. I appended the "gsw 1 2 .."
> > line (only one line) in the ESpice model of the
> capacitor.
> >
> > Thanks again all for the support.
> >
> > Regards.
> >
> > Hassan.
> >
> > On Mar 13, "C. Kumar" <kumarchi@xxxxxxxxx> wrote:
> > >
> > > try this.
> > >
> > > cdc 1 2 my_dccap
> > > gsw 1 2 i='if (time <= 0) (1e3 * v(1,2)) else 0'
> > >
> > > Patrick_Carrier@xxxxxxxx wrote:
> > > I agree with Lou. I know in Spice you can get
> around that anomaly by
> > > specifying an initial charge condition on the
> cap. I don't think there is a
> > > way to do that in Specctraquest though, so you
> need to just wait several
> > > cycles to look at the waveform.
> > >
> > > --Pat
> > >
> > > -----Original Message-----
> > > From: Sanchez, Louis
> [mailto:louis.sanchez@xxxxxxxxx]
> > > Sent: Wednesday, March 13, 2002 10:55 AM
> > > To: 'hassan@xxxxxxxx'; si-list@xxxxxxxxxxxxx
> > > Subject: [SI-LIST] Re: SPECCTRAQuest: DC level
> shift with series caps
> > >
> > >
> > >
> > > Hello Hassan............
> > >
> > > It will take several pulses before you see the
> expected results in an AC
> > > coupled network. I believe that you are dealing
> with the initial condition
> > > of time it takes for all storage elements
> (capacitors) to reach equilibrium.
> > > I suggest that you lengthen the period of your
> analysis in the Preferences
> > > section of SigXplorer.
> > >
> > > Lou A. Sanchez
> > >
> > > -----Original Message-----
> > > From: Hassan O. Ali [mailto:hassan@xxxxxxxx]
> > > Sent: Wednesday, March 13, 2002 6:49 AM
> > > To: si-list@xxxxxxxxxxxxx
> > > Subject: [SI-LIST] SPECCTRAQuest: DC level shift
> with series caps
> > >
> > >
> > >
> > > Hi All,
> > >
> > > I'm trying to use SigXplorer to simulate a link
> with a differential
> > > driver and series DC-blocking caps. Contrary to
> expectations,
> > > single-ended P and N outputs measured at the
> load are not centered
> > > around 0V DC, instead each one is given a
> separate DC shift. When I
> > > remove the series caps, the output is as
> expected - centered around 0V
> > > DC.
> > >
> > > Does anybody know what I can do to have the
> correct single-ended outputs
> > > with the series caps?
> > >
> > > Thanks.
> > >
> > > Hassan.
> > >
>
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