[SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps
- From: Hassan Ali <hassan@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 13 Mar 2002 20:47:34 -0500 (EST)
I forgot an opening quote. The lines should read:
g1 1 2 i='if (time <= 1e-10) (1e-6 * v(1,2)) else (1e4 * v(1,2))'
g2 3 2 i='if (time <= 1e-10) (1e4 * v(3,2)) else (1e-6 * v(3,2))'
Regards.
Hassan.
On Mar 13, Hassan Ali <hassan@xxxxxxxx> wrote:
>
>
> I toyed a little more with Kumar's idea. Here's the solution that works -
> without long
> simulation.
>
> Requirements: You need to know the common mode voltage at the driver output
> for the
corner
> (fast, typ, slow) case of interest. Call that "V_cm".
>
> 1. In SigXplorer, go to Analyse -> Libraries. Choose Model Browser, filter for
> ESpiceDevices, and click on any two-pin device (e.g. resistor50).
>
> 2. Click Add Model -> CloneSelection. Give a name to your clone e.g. "switch".
>
> 3. In the Model Browser now click on "switch" and then choose "Edit". A text
> editor will
> pop up.
>
> 4. Edit the model so that it reads as follows:
>
> ("switch"
> ("PinConnections"
> ("1" "2")
> ("2" "1")
> )
> ("ESpice"
> ".subckt switch 1 2
> g1 1 2 i=if (time <= 1e-10) (1e-6 * v(1,2)) else (1e4 * v(1,2))'
> g2 3 2 i=if (time <= 1e-10) (1e4 * v(3,2)) else (1e-6 * v(3,2))'
> Vcm 3 0 V_cm
> .ends switch
> ")
> ("Manufacturer" "myself")
> )
>
>
> Remember to replace V_cm with the actual common voltage value. Save the file
> when done.
>
> This ESpice element, all it does is to initialize the outputs to the
> common-mode voltage
> in the first 100ps of simulation. It does that by implementing two switches:
> one to the
DC
> source that initializes the outputs, and another to the signal that comes
> from the
driver.
>
> With respect to the driver signal, the switch is opened (resistance=1megaohm)
> in the
first
> 100ps and closed (resistance=0.1milliohm) after the first 100ps. It is
> viceversa for the
> DC source.
>
> 5. Close the model browser and close the Library browser by hitting OK.
>
> 6. Now place the "switch" ESpice device just before the DC-blocking cap -
> with pin 2
> connecting to the cap. For a differential link you'll have to have two of
> those devices
-
> one for each cap.
>
> 7. Simulate and see what happens.
>
>
> Hassan.
>
>
> On Mar 13, "Sanchez, Louis" <louis.sanchez@xxxxxxxxx> wrote:
> >
> > Hi Hassan..........
> >
> > I should mention that the length of time it takes (number of pulses) is a
> > function of the time constant formed by the Capacitance of the coupling
> > caps, and the resistance of the load. You can play with the value of either
> > the load resistance or the capacitance, and you should see the effect this
> > has on the length of time it takes for the signals to stabalize.
> >
> > Lou A. Sanchez
> > louis.sanchez@xxxxxxxxx
> >
> > -----Original Message-----
> > From: Hassan Ali [mailto:hassan@xxxxxxxx]
> > Sent: Wednesday, March 13, 2002 3:11 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps
> >
> >
> >
> > Thanks all for your suggestions.
> >
> > Actually, the sure way is that suggested by Lou - to run the simulation to
> > death!
> > Actually, in my case I had to run it for 2500 cycles!
> >
> > Kumar's trick is interesting. I tried it but it didn't really solve the
> > problem. I still
> > had to run the simulation for a long time to obtain 0V DC. I appended the
> > "gsw 1 2 .."
> > line (only one line) in the ESpice model of the capacitor.
> >
> > Thanks again all for the support.
> >
> > Regards.
> >
> > Hassan.
> >
> >
> > On Mar 13, "C. Kumar" <kumarchi@xxxxxxxxx> wrote:
> > >
> > > try this.
> > >
> > > cdc 1 2 my_dccap
> > > gsw 1 2 i='if (time <= 0) (1e3 * v(1,2)) else 0'
> > >
> > > Patrick_Carrier@xxxxxxxx wrote:
> > > I agree with Lou. I know in Spice you can get around that anomaly by
> > > specifying an initial charge condition on the cap. I don't think there is
> > a
> > > way to do that in Specctraquest though, so you need to just wait several
> > > cycles to look at the waveform.
> > >
> > > --Pat
> > >
> > > -----Original Message-----
> > > From: Sanchez, Louis [mailto:louis.sanchez@xxxxxxxxx]
> > > Sent: Wednesday, March 13, 2002 10:55 AM
> > > To: 'hassan@xxxxxxxx'; si-list@xxxxxxxxxxxxx
> > > Subject: [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps
> > >
> > >
> > >
> > > Hello Hassan............
> > >
> > > It will take several pulses before you see the expected results in an AC
> > > coupled network. I believe that you are dealing with the initial condition
> > > of time it takes for all storage elements (capacitors) to reach
> > equilibrium.
> > > I suggest that you lengthen the period of your analysis in the Preferences
> > > section of SigXplorer.
> > >
> > > Lou A. Sanchez
> > >
> > > -----Original Message-----
> > > From: Hassan O. Ali [mailto:hassan@xxxxxxxx]
> > > Sent: Wednesday, March 13, 2002 6:49 AM
> > > To: si-list@xxxxxxxxxxxxx
> > > Subject: [SI-LIST] SPECCTRAQuest: DC level shift with series caps
> > >
> > >
> > >
> > > Hi All,
> > >
> > > I'm trying to use SigXplorer to simulate a link with a differential
> > > driver and series DC-blocking caps. Contrary to expectations,
> > > single-ended P and N outputs measured at the load are not centered
> > > around 0V DC, instead each one is given a separate DC shift. When I
> > > remove the series caps, the output is as expected - centered around 0V
> > > DC.
> > >
> > > Does anybody know what I can do to have the correct single-ended outputs
> > > with the series caps?
> > >
> > > Thanks.
> > >
> > > Hassan.
>
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