[SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps

  • From: Alan Hilton-Nickel <ahilton@xxxxxxxxxxxxx>
  • To: hassan@xxxxxxxx
  • Date: Thu, 14 Mar 2002 09:16:00 -0800

Hassan,

I wondered if that might be the thing to do. It's also possible in simulation
(and indeed, frequent practice), to add the resistor I suggested to set a DC
level. In simulation it would be a very large value, such as 1 to 10Meg. It
should do the trick in at most a couple of cycles. This is another way of
implementing Kumar's suggestion of setting the initial charge condition on the
cap.

Also note that this effect is not necessarily a "simulation thing" - there is
some relationship to reality. If you have a cyclical signal, like a clock, you
should indeed get a 0 V DC level. But if it is data, a long string of "1"s or
"0"s will shift the DC level up or down. Even with a clock, a duty cycle that is
not exactly 50% can have a small offset. Try a 45% duty cycle in your simulation
and you'll see what I mean!

Alan Hilton-Nickel
Transmeta Corp.

Hassan Ali wrote:
> 
> Thanks all for your suggestions.
> 
> Actually, the sure way is that suggested by Lou - to run the simulation to 
> death!
> Actually, in my case I had to run it for 2500 cycles!
> 
> Kumar's trick is interesting. I tried it but it didn't really solve the 
> problem. I still
> had to run the simulation for a long time to obtain 0V DC. I appended the 
> "gsw 1 2 .."
> line (only one line) in the ESpice model of the capacitor.
> 
> Thanks again all for the support.
> 
> Regards.
> 
> Hassan.
> 
> On Mar 13, "C. Kumar" <kumarchi@xxxxxxxxx> wrote:
> >
> >  try this.
> >
> > cdc 1 2 my_dccap
> > gsw 1 2 i='if (time <= 0) (1e3 * v(1,2)) else 0'
> >
> >   Patrick_Carrier@xxxxxxxx wrote:
> > I agree with Lou. I know in Spice you can get around that anomaly by
> > specifying an initial charge condition on the cap. I don't think there is a
> > way to do that in Specctraquest though, so you need to just wait several
> > cycles to look at the waveform.
> >
> > --Pat
> >
> > -----Original Message-----
> > From: Sanchez, Louis [mailto:louis.sanchez@xxxxxxxxx]
> > Sent: Wednesday, March 13, 2002 10:55 AM
> > To: 'hassan@xxxxxxxx'; si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: SPECCTRAQuest: DC level shift with series caps
> >
> >
> >
> > Hello Hassan............
> >
> > It will take several pulses before you see the expected results in an AC
> > coupled network. I believe that you are dealing with the initial condition
> > of time it takes for all storage elements (capacitors) to reach equilibrium.
> > I suggest that you lengthen the period of your analysis in the Preferences
> > section of SigXplorer.
> >
> > Lou A. Sanchez
> >
> > -----Original Message-----
> > From: Hassan O. Ali [mailto:hassan@xxxxxxxx]
> > Sent: Wednesday, March 13, 2002 6:49 AM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] SPECCTRAQuest: DC level shift with series caps
> >
> >
> >
> > Hi All,
> >
> > I'm trying to use SigXplorer to simulate a link with a differential
> > driver and series DC-blocking caps. Contrary to expectations,
> > single-ended P and N outputs measured at the load are not centered
> > around 0V DC, instead each one is given a separate DC shift. When I
> > remove the series caps, the output is as expected - centered around 0V
> > DC.
> >
> > Does anybody know what I can do to have the correct single-ended outputs
> > with the series caps?
> >
> > Thanks.
> >
> > Hassan.
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> > <P>&nbsp;try this.
> > <P>&nbsp;
> > <P>cdc 1 2 my_dccap
> > <P>gsw 1 2 i='if (time &lt;= 0) (1e3 * v(1,2)) else 0'
> > <P>&nbsp;
> > <P>&nbsp; <B><I>Patrick_Carrier@xxxxxxxx</I></B> wrote:
> > <BLOCKQUOTE style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: 
> > #1010ff 2px
> solid"><BR>I agree with Lou. I know in Spice you can get around that anomaly
> by<BR>specifying an initial charge condition on the cap. I don't think there 
> is a<BR>way
> to do that in Specctraquest though, so you need to just wait 
> several<BR>cycles to look at
> the waveform.<BR><BR>--Pat<BR><BR>-----Original Message-----<BR>From: 
> Sanchez, Louis
> [mailto:louis.sanchez@xxxxxxxxx]<BR>Sent: Wednesday, March 13, 2002 10:55 
> AM<BR>To:
> 'hassan@xxxxxxxx'; si-list@xxxxxxxxxxxxx<BR>Subject: [SI-LIST] Re: 
> SPECCTRAQuest: DC level
> shift with series caps<BR><BR><BR><BR>Hello Hassan............<BR><BR>It will 
> take several
> pulses before you see the expected results in an AC<BR>coupled network. I 
> believe that you
> are dealing with the initial condition<BR>of time it takes for all storage 
> elements
> (capacitors) to reach equilibrium.<BR>I suggest that you lengthen the period 
> of your
> analysis in the Preferences<BR>section of SigXplorer.<BR><BR>Lou A.
> Sanchez<BR><BR>-----Original Message-----<BR>From: Hassan O. Ali
> [mailto:hassan@xxxxxxxx]<BR>Sent: Wednesday, March 13, 2002 6:49 AM<BR>To:
> si-list@xxxxxxxxxxxxx<BR>Subject: [SI-LIST] SPECCTRAQuest: DC level shift 
> with series
> caps<BR><BR><BR><BR>Hi All,<BR><BR>I'm trying to use SigXplorer to simulate a 
> link with a
> differential<BR>driver and series DC-blocking caps. Contrary to
> expectations,<BR>single-ended P and N outputs measured at the load are not
> centered<BR>around 0V DC, instead each one is given a separate DC shift. When 
> I<BR>remove
> the series caps, the output is as expected - centered around 
> 0V<BR>DC.<BR><BR>Does anybody
> know what I can do to have the correct single-ended outputs<BR>with the series
> caps?<BR><BR>Thanks.<BR><BR>Hassan.<BR>------------------------------------------------------------------<BR>To
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