My method of addressing this is to extract the PDN model of the layout with
localized ports (six ports at least, in this case - if not considering the
caps), then plug in the buck/VRM model. This way the ground/power bounce should
be able to be characterized.
Regards,
Sherman Shan Chen
SI/PI Group, Kandou Bus
5 Queensbridge, Northampton, UK, NN4 7BF
Office: +44 1604 635826 Email: shan@xxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf Of
Ivor Bowden
Sent: Tuesday, December 3, 2019 11:54 PM
To: si-list@xxxxxxxxxxxxx; agathon <hreidmarkailen@xxxxxxxxx>
Subject: [SI-LIST] Re: SMPS buck: behavioral model for high-side current noise
I've considered this before. It's not as simple as "noise on a high side plane".
Consider how bucks work.
When the buck high side FET is on, the current flows from VDD source to buck
VDD pin to buck Output pin through the inductor to the load, the return current
back to the VDD source ground. Inductor field builds.
When the buck high side FET is off (and low side FET on for synchronous bucks)
the current flows from buck GND pin to buck Output pin through the inductor to
the load, the return current back to the buck GND pin (due to inductor field
collapse).
When the buck switches, the current is "discontinuous", in that all the load
current is switched between buck VDD pin and buck GND pin. This results in
substantial noise on both the VDD and GND rails, depending on the PDN quality
e.g.
bypassing between them. Some physical buck circuits will measure noise spike
amplitudes of volt or more on both buck VDD and buck GND pins, with respect to
a "cleaner" ground, even e.g. only a few cm away. The concern is how much these
VDD and GND spikes show up on nearby devices' VDD and GND pins.
So to model a buck on a PDN, you could use two current sources, one (for high
side) between buck VDD pin and buck Output pin; the other (for low side)
between buck GND pin and buck Output pin. The two sources would need
trapezoidal edges to mimic buck output rise / fall times, typically range of
amps / nS, and they'd overlap so that the output current was a steady value.
Steady value would probably be fine for noise simulation, for more detail the
resultant current could also mimic the ripple current, e.g. 30% of steady state
current, say by using PWL current sources.
For this simulation, the inductor could be replaced by a short, or to add the
voltage noise of the buck Output pin switching to the system, model with
inductor. The load could be modeled by a resistor. The output voltage is of
course buck VDD * duty cycle (minus losses), which will also be buck average
output current times (modeled) load resistance.
This describes continuous mode steady state load simulation, not considering
load transient / buck transfer function.
For this example, you'd need to extract (3) ports: Buck VDD pin, Buck GND pin,
Buck Output pin, assuming that extraction already shorted the input power
connector, the inductor, and replaced load with resistor. Else, ports could be
extracted for them also, and shorts / components supplied in the simulation.
Then for the simulation you'd connect a switched current source between Buck
VDD port and Buck Output port, and connect a switched current source between
Buck GND port and Buck Output port, as described above.
Difficulty is what to use for the extraction port references, where should
their common ground be? Also extraction tool may have issues with a port (Buck
GND) being connected to the same physical net as its reference (ground).
It's the same problem trying to model "ground bounce" using a PCB extraction
and simulate dynamic loads on ground pins.
We know that "ground is not ground", over a given PCB there will be differences
in ground potentials, and sometimes those noise deltas can be significant to
the point of causing signal integrity problems, false clocking, etc. The bigger
question is how to model "ground bounce" across a PCB using extraction /
simulation tools.
Any ideas / tech notes about tool flows for these cases (ground bounce
simulation / SMPS simulation) appreciated.
Regards,
Ivor
On 11/26/2019 1:28 PM, agathon wrote:
Hello all,
I need to model noise on a high-side plane (feeding several SMPS).
I will extract a plane model but for the freq/time domain simulation...
My 2 challenges I can see are:
1) ferrite SMT model ...
but I see the si-list archive on this. They were nixed on the pcb
respin, anyway, but need to model their usage.
2) behavioral noise source that emulates SMPS constant-pwr current.
I don't need to model a particular part. Vendor models, I'm told,
don't operate at the pwm switching level, anyway.
My sense is that I only need a behavioral model that will act like
"constant power", so it simply switches current in and out and adjusts
voltage in lock step, like a buck SMPS. I'm thinking a pwl file for a
current waveform then a ICVS across it, parametrized to achieve
constant power.
Comments? And, if agreed, suggestions on common elements to do this?
Regards,
Reid
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
