Thank you agathon for the link, a good app note about
reducing EMI, and on page 28 / slide 29 showing discussion
extraction method. I see the suggested method is add to the
layout file before extraction a "Perfect Electrical
Conductor Cover" plane, covering entire PCB, 10mm away from
the rest of the electrical layers. This Cover is
(presumably) tied to PCB ground at only one point, e.g.
where the power connector is. This app note doesn't go into
further detail about placing ports including ground ports,
and assumption is all ports, including ground pins, have
their reference pins at the single common ground point that
is also tied to the Cover. Then the S-Parameters extracted
for simulation, in which noise on ground pins (with
reference to the single point / Cover ground) can be
observed. Apparently the Cover is an aid to the extraction
tool, the same setup could be used without defining the
Cover. Considering what the Cover effects are, how the
extraction results would differ with or without the cover,
or if the cover was some increased or decreased distance
from rest of layout. I may follow up with my Keysight rep
about this, and any perspectives and/or additional app notes
/ links about ground pins extractions for simulation (to
simulate / observe ground bounce / noise, etc.) are appreciated.
Thanks,
Ivor
On 12/15/2019 1:23 AM, Istvan Novak wrote:
Excellent slides, just one word of caution: whether it is
emission or susceptibility, the entire path matters. The
PCB is usually known, since it is our design. Bad
especially with power conversion circuits, the internal
current path in components and/or modules we place on the
board have typically way bigger vertical height above our
PCB planes compared to traces we place on the board.
Regards,
Istvan Novak
Samtec
On 12/15/2019 4:53 AM, agathon wrote:
See keysight.com and search for webcast on demand:
How to Reduce EMI in Switched-Mode Power Supplies with
Post-Layout
Simulation
The application is not the point. The pdf that comes with
it shows the
method on pdf p.28, slide29.
On Thu, Dec 12, 2019 at 7:07 PM Ivor Bowden
<bowden.ivor@xxxxxxxxx> wrote:
Any technical papers, app notes, etc. detailing this
type of
case / method?
Mainly tool setup / results with specific PCB example.
Physical measurements correlated with extraction /
simulation results would be a bonus.
Thanks,
Ivor
On 12/5/2019 8:55 AM, Scott McMorrow wrote:
Or, one can create a PEC reference plane in modeling, so
that power/ground port measurements can be referenced to
it.
It's as valid as matrices with partial inductance.
Scott McMorrow, CTO Signal Integrity Group
Samtec
Office 401-284-1827 | +1-800-726-8329
www.samtec.com
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On 12/5/2019 11:35 AM, Muranyi, Arpad wrote:
used since it combines the ground parasitics into ports'To characterize the effect of ground parasitics,
sparam may not be
parameters.
This statement is exactly why I posted my "tricksubject line
question" under the
"3d modelling of high frequency signals with dualdays ago.
referencing" a few
These two discussion topics are closely related becausecan tell).
both of them need
separate ports for the power and ground planes of the
board (as far as I
The problem I see is that many "PDN models" arethe
generated by combining
effects of both planes (as in a loop model), yet theto them
devices connected
need separate paths for the power and ground paths (asmodel).
in a partial
In this case, the above statement may be true.general, and
But, as Scott pointed out, this is not a limitation of
S-parameters in
for that reason, the above statement is not true independs on how
general. It all
the S-parameters are generated (extracted) and how theyModel
will be used.
makers and users need to be aware of those details,into the
otherwise we run
situation of trying to put a square peg into a round hole.ask
I just wanted to raise awareness to this, hoping to
encourage people to
themselves the right questions before making or usingOn Behalf Of Sherman Shan
S-parameter models.
It can just as easily be done correctly, as done
incorrectly...
Thanks,
Arpad
==============================================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
Sent: Thursday, December 5, 2019 10:42 AMhreidmarkailen@xxxxxxxxx>
To: bowden.ivor@xxxxxxxxx; si-list@xxxxxxxxxxxxx;
'agathon' <
Subject: [SI-LIST] Re: SMPS buck: behavioral model fornoise
high-side current
Ivor,since it combines the ground parasitics into ports'
To characterize the effect of ground parasitics, sparam
may not be used
parameters. One way to
separate the effect of ground is using RLGC matrix. The
six ports are
Vin_system, Vin_vrm, GND_vrm, Vo_vrm, Vo_load, and
GND_load. Make sense?
Regards,hreidmarkailen@xxxxxxxxx>
Sherman Shan Chen
SI/PI Group, Kandou Bus
5 Queensbridge, Northampton, UK, NN4 7BF
Office: +44 1604 635826 Email: shan@xxxxxxxxxx
-----Original Message-----
From: Ivor Bowden <bowden.ivor@xxxxxxxxx>
Sent: Thursday, December 5, 2019 11:14 AM
To: Sherman Shan <shan@xxxxxxxxxx>;
si-list@xxxxxxxxxxxxx; 'agathon' <
Subject: Re: [SI-LIST] Re: SMPS buck: behavioral modelcurrent noise
for high-side
Thank you Sherman,their associated reference points) for this example? Is
Please detail where you'd place the ports (for both the
signals and
it they all have
common reference e.g. at VDD connection GND, and the
signals are VDD input,
Buck VDD, Buck GND, Buck OUT, Load PWR, Load GND?
Thanks,with localized ports (six ports at least, in this case -
Ivor
On 12/4/2019 10:29 PM, Sherman Shan wrote:
My method of addressing this is to extract the PDN
model of the layout
if not considering
the caps), then plug in the buck/VRM model. This way the
ground/power
bounce should be able to be characterized.
side plane".Regards,
Sherman Shan Chen
SI/PI Group, Kandou Bus
5 Queensbridge, Northampton, UK, NN4 7BF
Office: +44 1604 635826 Email: shan@xxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
<si-list-bounce@xxxxxxxxxxxxx> On
Behalf Of Ivor Bowden
Sent: Tuesday, December 3, 2019 11:54 PM
To: si-list@xxxxxxxxxxxxx; agathon
<hreidmarkailen@xxxxxxxxx>
Subject: [SI-LIST] Re: SMPS buck: behavioral model for
high-side
current noise
I've considered this before. It's not as simple as
"noise on a high
buck VDD pin to buck Output pin through the inductor toConsider how bucks work.
When the buck high side FET is on, the current flows
from VDD source to
the load, the
return current back to the VDD source ground. Inductor
field builds.
bucks) the current flows from buck GND pin to buckWhen the buck high side FET is off (and low side FET
on for synchronous
Output pin through the
inductor to the load, the return current back to the
buck GND pin (due to
inductor field collapse).
load current is switched between buck VDD pin and buckWhen the buck switches, the current is
"discontinuous", in that all the
GND pin. This
results in substantial noise on both the VDD and GND
rails, depending on
the PDN quality e.g.
spike amplitudes of volt or more on both buck VDD andbypassing between them. Some physical buck circuits
will measure noise
buck GND pins, with
respect to a "cleaner" ground, even e.g. only a few cm
away. The concern is
how much these VDD and GND spikes show up on nearby
devices' VDD and GND
pins.
(for high side) between buck VDD pin and buck OutputSo to model a buck on a PDN, you could use two current
sources, one
pin; the other (for
low side) between buck GND pin and buck Output pin. The
two sources would
need trapezoidal edges to mimic buck output rise / fall
times, typically
range of amps / nS, and they'd overlap so that the
output current was a
steady value. Steady value would probably be fine for
noise simulation, for
more detail the resultant current could also mimic the
ripple current, e.g.
30% of steady state current, say by using PWL current
sources.
add the voltage noise of the buck Output pin switchingFor this simulation, the inductor could be replaced by
a short, or to
to the system, model
with inductor. The load could be modeled by a resistor.
The output voltage
is of course buck VDD * duty cycle (minus losses), which
will also be buck
average output current times (modeled) load resistance.
considering load transient / buck transfer function.This describes continuous mode steady state load
simulation, not
GND pin, Buck Output pin, assuming that extractionFor this example, you'd need to extract (3) ports:
Buck VDD pin, Buck
already shorted the
input power connector, the inductor, and replaced load
with resistor. Else,
ports could be extracted for them also, and shorts /
components supplied in
the simulation.
Buck VDD port and Buck Output port, and connect aThen for the simulation you'd connect a switched
current source between
switched current source
between Buck GND port and Buck Output port, as described
above.
should their common ground be? Also extraction tool mayDifficulty is what to use for the extraction port
references, where
have issues with a
port (Buck GND) being connected to the same physical net
as its reference
(ground).
extraction and simulate dynamic loads on ground pins.It's the same problem trying to model "ground bounce"
using a PCB
differences in ground potentials, and sometimes thoseWe know that "ground is not ground", over a given PCB
there will be
noise deltas can be
significant to the point of causing signal integrity
problems, false
clocking, etc. The bigger question is how to model
"ground bounce" across a
PCB using extraction / simulation tools.
simulation / SMPS simulation) appreciated.Any ideas / tech notes about tool flows for these
cases (ground bounce
non-public information.Regards,
Ivor
On 11/26/2019 1:28 PM, agathon wrote:
Hello all,------------------------------------------------------------------
I need to model noise on a high-side plane (feeding
several SMPS).
I will extract a plane model but for the freq/time
domain simulation...
My 2 challenges I can see are:
1) ferrite SMT model ...
but I see the si-list archive on this. They were
nixed on the pcb
respin, anyway, but need to model their usage.
2) behavioral noise source that emulates SMPS
constant-pwr current.
I don't need to model a particular part. Vendor
models, I'm told,
don't operate at the pwm switching level, anyway.
My sense is that I only need a behavioral model that
will act like
"constant power", so it simply switches current in
and out and
adjusts voltage in lock step, like a buck SMPS. I'm
thinking a pwl
file for a current waveform then a ICVS across it,
parametrized to
achieve constant power.
Comments? And, if agreed, suggestions on common
elements to do this?
Regards,
Reid
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