[SI-LIST] Re: SA12E Vil and Vih
- From: "D. C. Sessions" <si-list@xxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 7 Jan 2002 07:10:23 -0700
On Friday 04 January 2002 16:31, Jeremy Plunkett wrote:
# Mike,DC,Todd,Andy,
# Another important question underlies Mike's original question: is it
# appropriate to be using the AC Vil/Vih thresholds for a worst case timing
# analysis in the first place? Many bus specifications including HSTL and
# SSTL specify that all timing measurements should be taken at VREF. The AC
# thresholds are specified in order to ensure enough overdrive of the input
# comparator to switch at a predictable speed, and also may allow for
# threshold uncertainties inherent in the receiving device such as VREF noise,
# signal crosstalk, etc. However, the vendor must meet their timing in the
# JEDEC specified test environment and under "actual use conditions" with the
# signal crossing measured at VREF (and with the specified minimum input slew
# rate).
With all due respect, the discussion wasn't about taking timing at the
"thresholds." JEDEC specs are always written with timing relative to
Vref crossings, simply because anything else introduces rise/fall skews
that are lethal in source-synchronous systems (which is where these
specs were developed.)
I think I can speak with some authority on the subject of JEDEC
specifications ....
--
| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat. |
+--------------- D. C. Sessions <dcs@xxxxxxxxxxxxxxxx> --------------+
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