> # IBM specifies Vil and Vih for SA12E technology as 0.1V below and > above the reference voltage. But the JEDEC specification for the same > uses 0.2V above and below the reference. Any opinions on which values > to use for worst case timing analysis? >=20 > Mike, could you clarify the JEDEC spec in question? > SA12E isn't to my knowledge a JEDEC specification. > (JEDEC specs are JESD* ) >=20 >=20 (FYI - SA12E is an IBM Microelectronics ASIC product line.) Also, it would help if Mike were to clarify which SA12E buffer type has the Vih and Vil specs in question. AGP, CMOS, GTL, HSTL, PCI, SSTL, LVTTL? If IBM guarantees performance that is tighter than some other written spec, then you ought to be able to use the tighter specs guaranteed by the vendor, for input signals to the vendor's chip. But if you want to be truly worst case, use the looser specs. To some degree this choice depends on how much confidence you have that you have included everything in your simulations: power noise, crosstalk, how good your models are, etc. Regards, Andy ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu