[SI-LIST] Re: SA12E Vil and Vih
- From: "Lynne Green" <lgreen@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 8 Jan 2002 16:05:18 -0500
My I/O design experience was that designing 3.3V I/O over all
process/temperature/power supply variations did indeed lead to
receiver logic thresholds (even at DC) that were worst-case=20
within ~20-30 mV of Vinh and Vinl.
Back in the good old days (about 2 years ago), the "delay" used
for chip timing analysis for I/O circuits could be assigned to the=20
"board" or the "chip" timing (and novice designers always assumed
it was done in the other one). To make matters more interesting,
board designers and I/O designers (and I/O standard cell designers)
can (and often do) use different reference voltages for their timing
simulations, leading to increased timing uncertainty.
Back then, experienced designers had the habit of leaving a safety=20
margin ("padding") in timing allowances. Unfortunately, today the
total clock cycle is >10x faster than our old rule-of-thumb padding.
Sigh...
- Lynne
"All the world's an analog stage, whereon digital plays bit parts."
Andrew.Ingraham@xxxxxxxxxx> wrote:
There are various reasons why a different edge rate causes the timings
to change. One is that the input buffer has some unpredictable input
offset voltage, so the actual "switch point" might be anywhere between
Vil and Vih (an oversimplification, perhaps, but let's use it anyway).
Another is gain bandwidth product. Even if the input buffer had no
offset voltage, its response time still depends on overdrive.
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