[SI-LIST] Re: Routing guidelines for 3.12Gbps LVDS pairs
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
- Date: Tue, 20 Oct 2009 07:43:28 -0700
Lee, If the driver is really slow or the path very long that might be
OK. For a clean driver on modest length links, 50ps skew can run 50% or
more of Tr/Tf. I don't like that much mode conversion.
Best Regards,
Steve.
Lee Ritchey wrote:
> Actually, I was being conservative at 100 mils. A mismatch of 300 mils
> total is acceptable throughout the total path. 300 mils is roughly 50
> pSec.out of a 320 pSec bit interval.
>
>
>
>> [Original Message]
>> From: Peterson, James F (EHCOE) <james.f.peterson@xxxxxxxxxxxxx>
>> To: <si-list@xxxxxxxxxxxxx>
>> Date: 10/20/2009 6:09:07 AM
>> Subject: [SI-LIST] Re: Routing guidelines for 3.12Gbps LVDS pairs
>>
>> One comment on length matching at 100 mils : a lot of times the board
>> we're looking at is only one section of the interface. There is often
>> two more boards involved (a backplane and endpoint). When we say 100
>> mils matched lengths, are we saying total matched length or at each
>> board (so total could be 300 mils in that case)? The thread below says
>> "matched at the receiver", which implies total, so the 100 mils should
>> be budgeted through 3 boards.
>>
>> Regards,
>> Jim Peterson
>> Honeywell
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of steve weir
>> Sent: Tuesday, October 20, 2009 1:13 AM
>> To: icer world
>> Cc: Lee Ritchey; Paul Hurst; si-list@xxxxxxxxxxxxx; chundi srikanth;
>> Lambert Simonovich
>> Subject: [SI-LIST] Re: Routing guidelines for 3.12Gbps LVDS pairs
>>
>> 1) Matching much closer than 1/4 Tr/Tf offers little value by itself.
>> 100mils translates to about 16ps skew. That corresponds to a 64ns Tr/Tf
>>
>> for a 3.125G link which is a little to the outside, but it is not
>> horrible. I would rephrase Lee's advice as: Don't take any
>> extraordinary measures to match closer than 1/4 Tr/Tf as seen at the
>> receiver. The longer the link, the slower Tr/Tf will be. There is a
>> good treatment on this in Eric Bogatin's "Signal Integrity Simplified".
>>
>> If you get very tight matching truly for free, then fine. But obsessing
>>
>> about mechanical match to tight tolerances does not improve the design.
>>
>> It can in fact harm it if the matching is done with dense serpentines
>> which introduce their own dispersion and timing skew that is not
>> properly accounted in some tools.
>>
>> 2) Continuous return path is very important. Diff tolerates obscenities
>>
>> like crossing moats, but at undesirable costs. The best answer is don't
>>
>> interrupt the return path.
>>
>> 3) Surface ground guards are more often unintended resonators than of
>> specific value. See if the cross-talk can be satisfied with spacing.
>> If it can't, then consider alternatives.
>>
>> 4) I am not clear on what you are trying to recommend. Are you talking
>> about termination at both ends of the link, or even and odd mode
>> terminations?
>>
>> 5) An appropriate stitch density helps with EMC and signal integrity.
>> Follow Bruce Archambeault's hierarchy on layer assignments and your life
>>
>> will be good:
>> i. Route on one layer that faces a contiguous plane.
>> ii. Switch between layers on either side of the same contiguous plane.
>> iii. Switch between layers that reference planes on the same DC
>> potential that are adequately stitched together. This is often
>> misunderstood as needing to assign a return stitch via near each
>> transition. The point is to raise the resonant frequency of the
>> structure sufficiently so that it won't be a problem to the signal.
>> iv. If you must switch between layers that are stitched with bypass caps
>>
>> and planar capacitance. Be wary of PDN resonances in the signal
>> frequency range. These will tend to occur at much lower frequency than
>> cavity resonances.
>>
>> Steve.
>>
>> icer world wrote:
>>
>>> 1) length matching must be consided seriously and mismatch should be
>>>
>> below 100mils;
>>
>>> 2) generally speaking,the differential pairs impedance must keep
>>>
>> 100ohm and the ground return path must not be choped ;
>>
>>> 3) the ground guarding trace should keep two times of differential
>>>
>> trace width away from the differantial pairs,which can not influences
>> the differential pairs impedance and avoid crosstalk issues;
>>
>>> 4) using serial and parallel matching resistors simultaneously for
>>>
>> debug ;
>>
>>> 5) changing layers is not expected,but if necessary ,you should place
>>>
>> a groung via near the signal via ;
>>
>>> the above is just an advice ,and you'd better do a simulatiom to
>>>
>> decide the rules of matching resistors and crosstalk;
>>
>>>
>>> ________________________________
>>> From: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
>>> To: Paul Hurst <paul@xxxxxxxxxxxxxxxxxxxxxx>; si-list@xxxxxxxxxxxxx
>>> Cc: chundi srikanth <chundis@xxxxxxxxx>; Lambert Simonovich
>>>
>> <bertsimonovich@xxxxxxxxxx>
>>
>>> Sent: Mon, October 19, 2009 11:46:36 PM
>>> Subject: [SI-LIST] Re: Routing guidelines for 3.12Gbps LVDS pairs
>>>
>>> Length matching does not need to be tighter than 100 mils.
>>>
>>> It is not necessary to back drill vias used to connect component pins
>>>
>> to
>>
>>> traces or to change layers. The 0.6 pF or so capacitance does not
>>> adversely affect the signals at this data rate.
>>>
>>> It is not necessary to put "ground" vias next to routing vias as long
>>>
>> as
>>
>>> the PDS is well designed."
>>>
>>> "Guard" traces have no value. Proper spacing to avoid crosstalk
>>>
>> does.
>>
>>> The "rule of thumb" for spacing given, while crude, is not far off.
>>>
>>> Lee Ritchey
>>>
>>>
>>>
>>>
>>>> [Original Message]
>>>> From: Paul Hurst <paul@xxxxxxxxxxxxxxxxxxxxxx>
>>>> To: <si-list@xxxxxxxxxxxxx>
>>>> Cc: chundi srikanth <chundis@xxxxxxxxx>; Lambert Simonovich
>>>>
>>>>
>>> <bertsimonovich@xxxxxxxxxx>
>>>
>>>
>>>> Date: 10/18/2009 5:45:08 PM
>>>> Subject: [SI-LIST] Re: Routing guidelines for 3.12Gbps LVDS pairs
>>>>
>>>> Srikanth,
>>>>
>>>> Additional to Bert's comments:-
>>>>
>>>> 1) Match the lengths of the pairs exactly
>>>> 2) Use a solid ground return
>>>> 3) Avoid stubs by design or by using stub-drilling
>>>> 4) If you have vias in the path use a small drill and a large
>>>>
>> anti-pad and
>>
>>>> place a ground via next to each signal via
>>>>
>>>> Regards
>>>>
>>>> Paul
>>>>
>>>> -----Original Message-----
>>>> From: si-list-bounce@xxxxxxxxxxxxx
>>>>
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>
>>>>
>>>>
>>> On
>>>
>>>
>>>> Behalf Of Lambert Simonovich
>>>> Sent: 16 October 2009 21:57
>>>> To: 'chundi srikanth'; si-list@xxxxxxxxxxxxx
>>>> Subject: [SI-LIST] Re: Routing guidelines for 3.12Gbps LVDS pairs
>>>>
>>>>
>>>> Srikanth,
>>>>
>>>> A rough rule of thumb is greater than 3 times trace width separation
>>>>
>>>>
>>> between
>>>
>>>
>>>> pairs. Using a 2D field solver will ultimately give you the crosstalk
>>>> coupling factor for the exact geometry in your stackup, and dictate
>>>>
>> the
>>
>>>> routing rules you need to follow to satisfy your noise budget.
>>>>
>>>> Adding GND guarding will more often than not present more issues than
>>>>
>> it
>>
>>>> solves. You should stitch these guard traces at regular intervals
>>>> approximately 1/10 of the wavelength of the highest frequency
>>>>
>> component of
>>
>>>> the aggressor signal to avoid it from resonating and coupling noise
>>>>
>> back
>>
>>>> onto other adjacent traces. This further reduces routing density of
>>>>
>> the
>>
>>>> board. By the time you factor in the additional space of one trace
>>>>
>> width
>>
>>>> between the guard trace and Diff pair, plus the additional via
>>>>
>> stitching,
>>
>>>> you will find you are already at 3 times separation between pairs and
>>>>
>> you
>>
>>>> would gain back more real estate.
>>>>
>>>> Regards,
>>>>
>>>> Bert Simonovich
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> -----Original Message-----
>>>> From: si-list-bounce@xxxxxxxxxxxxx
>>>>
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>
>>>>
>>>>
>>> On
>>>
>>>
>>>> Behalf Of chundi srikanth
>>>> Sent: October-16-09 12:40 PM
>>>> To: si-list@xxxxxxxxxxxxx
>>>> Subject: [SI-LIST] Routing guidelines for 3.12Gbps LVDS pairs
>>>>
>>>> Hi Techies,
>>>> We have a 12-layer board in which we have lot of differential LVDS
>>>>
>> pairs
>>
>>>> operating at several hundreds MHz. And we have SERDES signals
>>>>
>>>>
>>> (differential
>>>
>>>
>>>> TX & RX pairs) operating at CPRI rate-4 i.e., 3Gbps. So can you just
>>>>
>> share
>>
>>>> me some inputs on exactly what are the guidelines to be followed
>>>>
>> while
>>
>>>> routing these signals. And is GND gaurding between the differential
>>>>
>> pairs
>>
>>>> improve the SI?Please share or refer me any documents in which i can
>>>>
>> get
>>
>>>> Good information on High-Speed design guidelines.
>>>>
>>>> Thanks
>>>>
>>>> With Best Regards
>>>> Srikanth
>>>>
>>>>
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>> --
>> Steve Weir
>> IPBLOX, LLC
>> 150 N. Center St. #211
>> Reno, NV 89501
>> (866) 675-4630 Business
>> (707) 780-1951 Fax
>> http://www.ipblox.com
>> A Teraspeed Consulting Group LLC Partner
>>
>> Teraspeed Consulting Group
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>>
>> Teraspeed Labs
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IPBLOX, LLC
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Reno, NV 89501
(866) 675-4630 Business
(707) 780-1951 Fax
http://www.ipblox.com
A Teraspeed Consulting Group LLC Partner
Teraspeed Consulting Group
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
Teraspeed Labs
13610 SW Harness Lane
Beaverton, OR 97008
(503) 430-1065 Business
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A Teraspeed Consulting Group LLC Partner
http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of
IPBLOX LLC
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