[SI-LIST] Re: Routing High Speed over partial GND & partial split plane references
- From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- To: "Joseph.Rubinstein@xxxxxxx" <Joseph.Rubinstein@xxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 12 Dec 2012 22:21:59 +0000
Based on my experience, if you built this board as you describe, this is what I
believe you would observe in the lab:
1) Unless you use pathologically wide (>>10 mils) splits between your power
planes, you won't be able to discern the impedance variation due to crossing
the plane splits with a 20ps TDR, which is a must faster risetime than your
signals will actually see at that point.
a) I believe this is true for both your single-ended and DDR signals
2) Likewise, you won't be able to measure a significant difference in xtalk
with a TDR (or VNA)
a) I believe this is true for both your single-ended and DDR signals
3) On the other hand, if you have noise on your power planes, that noise will
be dramatically induced on both your single-ended and differential signals
a) For single-ended signals, this can easily be a killer
b) For differential signals, this "shouldn't" be an issue, though I've
personally experienced an instance where excessive common mode voltage induced
onto a clock signal caused errors in a PCIe device
I welcome others' well documented data which conflicts with this. Experiments
I've personally performed and/or designs I've been involved with have led me to
these conclusions, but of course I haven't experienced every possible scenario.
And now you've given me the impetus to try another experiment to further check
this assumption - will keep you informed.
I believe the fundamental physics are that the signal doesn't know whether that
adjacent piece of copper is "Ground", "VDDQ", or a floating piece of metal, and
doesn't care. If the piece of metal is close enough to make a significant
impact on your impedance, there is enough inter-plane capacitance to allow the
return current to flow between it and the "Ground" plane with little
perturbation. On the other hand, if a big piece of copper adjacent to a signal
has lots of noise on it, that noise will be very efficiently coupled onto your
traces.
I originally confronted this dilemma clear back in '01, and below is a synopsis
of what I posted in this forum back then. Nothing I've experienced since has
led me to change my opinions, except now I'm very aware that traces next to
voltage planes will pick up noise on those planes very readily.
I TDR'ed a board with symmetrical stripline (5mil wide trace 7 mils above
ground and 7 mils below Vcc) and measured its impedance:
(1) with the probe referenced to GND,
(2) referenced to VCC, and
(3) with GND and VCC shorted together (at the launch).
I saw no substantial difference between the 3 cases. Even slowed down the
rise-time to 400pS; no difference. I wondered if, by definition of stripline,
there isn't enough capacitance between the planes that the return current has a
low impedance path to the reference plane. I.E., TDR'ing between the 2 planes
shows a dead short - no need for external caps (or a shorting bar, in my case).
This worked until I thought of the case of asymmetrical stripline - would the
impedance measured depend on which plane you were referenced to? So, I built
myself some crude asymmetric stripline (using a TDR characterization board from
TEK as a starting point).
I took a microstrip trace and added a layer of Kapton tape over it, with a
sheet of copper over that. This turned the microstrip into a stripline, with
the 2nd plane floating. I TDR'ed the trace relative to Gnd, then relative to
the floating plane, and with the planes shorted together at the source (again,
relative to Gnd and the floating plane).
I then added another layer of Kapton tape between the trace and the floating
plane, and repeated the measurements.
I did this until I had 8 layers of Kapton tape between the trace and the
floating plane.
Granted, this was a pretty crude experiment and there were clearly some
measurement errors, but some things were pretty obvious. I would be interested
to hear where my findings and/or conclusions violate e-mag theory.
Findings:
1) Regardless of the Kapton thickness, the lower impedance measured (referenced
to Gnd or the floating plane) was approximately the same as that as when the
planes were shorted together.
2) With thin dielectrics (in the range that we typically use, < 7mils), the
impedance was approximately the same regardless of which plane was used as a
reference, and whether they were shorted together at the source.
Conclusions:
1) When TDR'ing stripline, it probably won't matter which plane we use as
reference. If in doubt, I would TDR relative to whichever plane was closest to
the trace. If still not convinced, I would short the 2 planes together
at the source.
2) I would ensure that, when using stripline with both power and ground planes,
the trace is closer to ground than power. This is assuming the signal is
routed relative to ground elsewhere.
3) I believe that a correct model for what I'm seeing is - it's the parallel
combination of Trace-to-Plane1, Trace-to-Plane1, and Plane-to-Plane impedances
that makes up the final impedance for a trace, relative to either Plane1 or
Plane2.
I hope this helps,
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Rubinstein, Joseph
Sent: Wednesday, December 12, 2012 9:58 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Routing High Speed over partial GND & partial split plane
references
Question:
Everyone knows the ideal way to reference a high speed signal/diff pair is to
have it coupled directly to a solid ground plane for the entire length of the
trace. I currently have a board in CAD and this is how some of my routes are
referenced.
My stack up for example has:
L5 - A solid ground plane
L6 - Signal, with some 6G high speed differential and some DDR3.
L7 - Power plane with splits.
L6 is equal distance from L5 and L7. If L5 and L7 were both solid ground
planes I would expect half of the return current to flow on L5 and half on L7.
I have 6G diff pairs and DDR3 busses routed across splits on the power layer.
My first reaction was this is a problem that needs fixing. As I thought about
it, If the path of least resistance for the return current is mostly on L5, the
solid ground plane, will the L7 layer not be seen as a discontinuity?
Thoughts?
Thanks
Joe
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