[SI-LIST] Re: Routing High Speed over partial GND & partial split plane references
- From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- To: "Joseph.Rubinstein@xxxxxxx" <Joseph.Rubinstein@xxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 13 Dec 2012 17:58:59 +0000
I got some off-line responses which cited two possible errors in my
expectations:
1) Increased cross-talk, especially when several aggressors are switching at
once - I'll deal with this in-depth farther below.
2) Resonance of the split plane. By this, I assume they mean the resonance of
the VDDQ plane shape. For this, I have experience which somewhat agrees. I
have seen instances where:
a) A floating piece of conductor (think heat sink or backing plate)
placed above microstrip traces has resonated nicely (badly) and wreaked havoc
in the system. But I think this was quite unlike what we're describing in this
instance. It was a very large shape, covering very many traces.
b) A VDDQ plane shape used as the only reference under DDR microstrip
traces was only tied to a few VDDQ vias at its endpoints, wandered around
between those endpoints to follow the traces, and had a lot of noise on it,
degrading the margins of the DDR significantly. But I think this was a rather
pathological case, again quite unlike what we're describing in this instance.
In my experience, I have not seen an instance where a reasonably shaped PCB
VDDQ plane resonated - I welcome others' documentation where that happened;
that might also give us insights into how to avoid this particular problem for
scenarios similar to Joe's (or for the scenario where the secondary plane is
relatively far away - that is still susceptible to this effect).
I would highlight that, in my experience, if the VDDQ plane has noise on it for
ANY reason (resonance, or proximity to a high current usage point, for
instance), that noise will be strongly impinged on the signals. This is
proportional to the distance between the plane and the traces, hence my
reluctance to put traces close to power shapes of any kind, including planes.
To test the increased crosstalk theory, I conducted an experiment to mimic that
effect (which most anyone with a TDR can duplicate). I've put a ppt which has
the waveforms at:
https://www.filesanywhere.com/fs/v.aspx?v=8a72678a5b6470b5a3ac
I had a test board with a long length (~13.5", or 343mm) of a microstrip
differential pair which I believe mimics an aggressor-victim pair.
* I TDR'ed the traces single-endedly w/o modification as a "baseline",
observing the waveforms at the 4 ports as TDR, TDT, NEXT, and FEXT. As
expected for microstrip w/ lots of coupling, there was significant NEXT and
FEXT. (see slide 5 of the ppt, purple waveforms, "baseline")
I then put a strip of copper tape over a portion of the microstrip traces, to
mimic a VDDQ plane adjacent to the signal traces which are referenced to "GND".
There was no DC connection between this copper shape and "GND". The copper
tape is very close to the traces (thickness of the soldermask), probably quite
a bit closer than the traces are to the "GND" plane (dielectric thickness
probably about 5 mils).
* Again, I TDR'ed the traces single-endedly. As expected for stripline, FEXT
was dramatically reduced, NEXT was somewhat reduced for the portion under the
copper tape. (see slide 5 of the ppt, green waveforms, "1Cu")
I then cut off a portion the copper tape with scissors - nothing very precise.
* This reduced the length of stripline portion, increasing FEXT, and changing
the time at which NEXT decreased. (see slide 5 of the ppt, blue waveforms,
"1aCu")
I then replaced the portion of tape I had cut off, very close, but probably not
closer than our typical 5-10 mil gap between shapes, to that which was still on
the board. I checked that there was no DC continuity between the two copper
tape shapes. This mimicked (to my mind) a VDDQ plane split between 2 VDDQ
shapes.
* TDR'ing this (see slides 2 & 3, red waveforms, "2Cu") and comparing it to
that of a single plane (slides 2 & 3, green waveforms, "1Cu") showed:
* The difference in TDR was slight, and I attribute the difference to
the slight differences in how the tape was applied (it is not going to sit down
as well after being peeled off and reapplied)
* Similar small differences in NEXT
* Very slight, but measureable, differences in FEXT and Tp. While
measureable, I consider the difference in FEXT to be insignificant. I also
don't know if the trend would continue if I tried this many times.
* Perhaps this would be grossly exacerbated by TDR'ing many signals
simultaneously, but I'm skeptical. When I tried to mimic that in the past for
similar scenarios, I have not been successful.
Again, I welcome others' documentation which indicates increased FEXT should be
expected for Joe's scenario.
Finally, if you're wondering why a floating piece of copper can act as a return
path with no DC connectivity, I would urge you to TDR (in your mind or
physically) between "GND" and a big, floating copper shape which is reasonably
close to that "GND" shape. I believe you'll find that it's a virtual short for
AC. If you wait long enough, it will begin to behave as a standard capacitor,
with the time vs. voltage following the classic curve we're familiar with. But
that takes a very long time, many UI's of time.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Loyer, Jeff
Sent: Wednesday, December 12, 2012 2:22 PM
To: Joseph.Rubinstein@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Routing High Speed over partial GND & partial split
plane references
Based on my experience, if you built this board as you describe, this is what I
believe you would observe in the lab:
1) Unless you use pathologically wide (>>10 mils) splits between your power
planes, you won't be able to discern the impedance variation due to crossing
the plane splits with a 20ps TDR, which is a must faster risetime than your
signals will actually see at that point.
a) I believe this is true for both your single-ended and DDR signals
2) Likewise, you won't be able to measure a significant difference in xtalk
with a TDR (or VNA)
a) I believe this is true for both your single-ended and DDR signals
3) On the other hand, if you have noise on your power planes, that noise will
be dramatically induced on both your single-ended and differential signals
a) For single-ended signals, this can easily be a killer
b) For differential signals, this "shouldn't" be an issue, though I've
personally experienced an instance where excessive common mode voltage induced
onto a clock signal caused errors in a PCIe device I welcome others' well
documented data which conflicts with this. Experiments I've personally
performed and/or designs I've been involved with have led me to these
conclusions, but of course I haven't experienced every possible scenario.
And now you've given me the impetus to try another experiment to further check
this assumption - will keep you informed.
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