[SI-LIST] Re: Rise/Fall time Vs Bit rate.
- From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
- To: emcesd@xxxxxxx
- Date: Tue, 28 Aug 2012 07:12:18 -0400
Tesla,
This Intel paper was at DesignCon 2009, titled
"Switching Voltage Regulator Noise Coupling Analysis for
Printed Circuit Board Systems" by Amy Luoh, Gene Garrison and Jon Powell.
BTW low-speed buses often fail because people focus on the most
challenging, highest-speed interconnects and then time runs out in the
design schedule.
Best regards,
Istvan Novak
Oracle
On 8/28/2012 6:00 AM, Tesla wrote:
> Hi, Steve
>
> Thanks a lot
>
> Would you give a link about the intel paper you mentioned? Be interested to
> read it.
>
> Regards.
>
> Tesla
>
>
>
>
> At 2012-08-28 16:15:37,"steve weir" <weirsi@xxxxxxxxxx> wrote:
>> If one is dealing with data signals, then as long as they settle out at
>> valid logic levels by the time they are sampled, and remain stable long
>> enough to satisfy hold time requirements, then all is good. That
>> observation has lulled many a digital engineer into "Sauron's Happy
>> Fun-Time Intermittent Failure Party at Mount Doom"(tm) when they neglect
>> the fact that not all low-rate signals are data. Some low-rate signals
>> are timing strobes, such as TCLK on a JTAG bus. Timing strobes not only
>> have to settle-out at valid levels, they need to be free of waveform
>> artifacts like double transitions.
>>
>> Then there are high impedance dinosaur busses that say: "Hey sailor:
>> For $20 dollars I'll take your induced noise around the world." A few
>> years ago Intel presented a DesignCon paper where they described
>> spending the better part of a million dollars on manpower and
>> sophisticated software tools, as well as nearly half a year tracking
>> down signal integrity problems on a lowly I2C bus. Every month or two
>> induced noise would cause servers to reset.
>>
>> Steve.
>>
>>
>> On 8/28/2012 12:23 AM, Rohit MISHRA wrote:
>>> Rajneesh,
>>>
>>> That's a good question, indeed !!
>>>
>>> You rightly pointed out that slow repetition pulses driven by fast driver
>>> can also have reflections & other transmission line effects but you should
>>> also understand that these effects create signal integrity problems most
>>> when they have less time to settle.
>>>
>>> The signal pulse width and duty cycle are not factors in deciding
>>> transmission line behavior such as reflections but when you use high pulse
>>> width i.e. low bit rate signal, you are also giving more time to settle
>>> these effects before sampling at receiver end and remember, what the signal
>>> looks like at sampling that matters most !
>>>
>>> Hope that helps.
>>>
>>>
>>> Rohit Mishra
>>>
>>>
>>>
>>> -----Original Message-----
>>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>>> Behalf Of rajneesh shukla
>>> Sent: Tuesday, August 28, 2012 12:29 PM
>>> To: si-list@xxxxxxxxxxxxx
>>> Subject: [SI-LIST] Rise/Fall time Vs Bit rate.
>>>
>>> Experts,
>>> We all have read that in high speed design it's rise time that creates
>>> signal integrity issue. By this theory, all low bit rate signals that
>>> is driven by fast I/O driver will also have signal integrity issues then
>>> why most of the time high bit rate signals are analysed for signal
>>> integrity issue ??
>>>
>>> Please explain what is the role of bit rate in signal integrity ??
>>>
>>> Rajneesh
>>>
>>>
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>>
>> --
>> Steve Weir
>> IPBLOX, LLC
>> 150 N. Center St. #211
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