[SI-LIST] Re: Rise/Fall time Vs Bit rate.
- From: rajneesh shukla <rajneeshs123@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 29 Aug 2012 19:56:10 +0530
Thanks Steve, Rohit & everyone for clearing my doubt.
So if I understood it right, if low bit rate signal is data signal then
chances of SI problem will be minimal but if it's strobe or reset signal
then we must analyse it for SI problem.
As a follow-up question...I would like to know how to handle SI problem in
low bit rate signals like strobe or reset signal. do we need to take some
special precaution or just need to have controlled impedance & resistive
termination ? I don't think that I have ever seen resistive termination in
reset/strobe signal.
rajneesh
On Wed, Aug 29, 2012 at 7:00 PM, Faraydon Pakbaz <pakbazf@xxxxxxxxxx> wrote:
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>
> Hi Istvan, Tesla;
>
> If I am not mistaken this is the paper than Istvan had in mind. It was
> presented in designcon 2009.
>
> "Switching Voltage Regulator Noise Coupling Analysis for Printed Circui=
> t
> Board Systems"
> Amy Luoh, Gene Garrison, Jon Powell
>
> Regards;
>
> Don Pakbaz
>
>
>
>
> |------------>
> | From: |
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> |Tesla <emcesd@xxxxxxx> =
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> | To: |
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> -------|
> |"Istvan Novak" <istvan.novak@xxxxxxxxxxx> =
> =
> |
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> |------------>
> | Cc: |
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> |weirsi@xxxxxxxxxx, si-list@xxxxxxxxxxxxx =
> =
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> >--------------------------------------------------------------------=
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> | Date: |
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> |08/29/2012 02:43 AM =
> =
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> | Subject: |
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> |[SI-LIST] Re: Rise/Fall time Vs Bit rate. =
> =
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> | Sent by: |
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>
>
>
>
>
> Hi, Istvan
>
> Thanks a lot.
> it is a long time that there is no update on your website......
>
> Regards.
>
> Tesla.
>
>
>
>
> At 2012-08-28 19:12:18,"Istvan Novak" <istvan.novak@xxxxxxxxxxx> wrote:=
>
> >Tesla,
> >
> >This Intel paper was at DesignCon 2009, titled
> >"Switching Voltage Regulator Noise Coupling Analysis for
> >Printed Circuit Board Systems" by Amy Luoh, Gene Garrison and Jon Powe=
> ll.
> >
> >BTW low-speed buses often fail because people focus on the most
> >challenging, highest-speed interconnects and then time runs out in the=
>
> >design schedule.
> >
> >Best regards,
> >
> >Istvan Novak
> >Oracle
> >
> >
> >On 8/28/2012 6:00 AM, Tesla wrote:
> >> Hi, Steve
> >>
> >> Thanks a lot
> >>
> >> Would you give a link about the intel paper you mentioned? Be intere=
> sted
> to read it.
> >>
> >> Regards.
> >>
> >> Tesla
> >>
> >>
> >>
> >>
> >> At 2012-08-28 16:15:37,"steve weir" <weirsi@xxxxxxxxxx> wrote:
> >>> If one is dealing with data signals, then as long as they settle ou=
> t at
> >>> valid logic levels by the time they are sampled, and remain stable =
> long
> >>> enough to satisfy hold time requirements, then all is good. That
> >>> observation has lulled many a digital engineer into "Sauron's Happy=
>
> >>> Fun-Time Intermittent Failure Party at Mount Doom"(tm) when they
> neglect
> >>> the fact that not all low-rate signals are data. Some low-rate sig=
> nals
> >>> are timing strobes, such as TCLK on a JTAG bus. Timing strobes not=
>
> only
> >>> have to settle-out at valid levels, they need to be free of wavefor=
> m
> >>> artifacts like double transitions.
> >>>
> >>> Then there are high impedance dinosaur busses that say: "Hey sailo=
> r:
> >>> For $20 dollars I'll take your induced noise around the world." A =
> few
> >>> years ago Intel presented a DesignCon paper where they described
> >>> spending the better part of a million dollars on manpower and
> >>> sophisticated software tools, as well as nearly half a year trackin=
> g
> >>> down signal integrity problems on a lowly I2C bus. Every month or =
> two
> >>> induced noise would cause servers to reset.
> >>>
> >>> Steve.
> >>>
> >>>
> >>> On 8/28/2012 12:23 AM, Rohit MISHRA wrote:
> >>>> Rajneesh,
> >>>>
> >>>> That's a good question, indeed !!
> >>>>
> >>>> You rightly pointed out that slow repetition pulses driven by fast=
>
> driver can also have reflections & other transmission line effects but =
> you
> should also understand that these effects create signal integrity probl=
> ems
> most when they have less time to settle.
> >>>>
> >>>> The signal pulse width and duty cycle are not factors in deciding
> transmission line behavior such as reflections but when you use high pu=
> lse
> width i.e. low bit rate signal, you are also giving more time to settle=
>
> these effects before sampling at receiver end and remember, what the si=
> gnal
> looks like at sampling that matters most !
> >>>>
> >>>> Hope that helps.
> >>>>
> >>>>
> >>>> Rohit Mishra
> >>>>
> >>>>
> >>>>
> >>>> -----Original Message-----
> >>>> From: si-list-bounce@xxxxxxxxxxxxx [
> mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of rajneesh shukla
> >>>> Sent: Tuesday, August 28, 2012 12:29 PM
> >>>> To: si-list@xxxxxxxxxxxxx
> >>>> Subject: [SI-LIST] Rise/Fall time Vs Bit rate.
> >>>>
> >>>> Experts,
> >>>> We all have read that in high speed design it's rise time that cre=
> ates
> >>>> signal integrity issue. By this theory, all low bit rate signals t=
> hat
> >>>> is driven by fast I/O driver will also have signal integrity issue=
> s
> then
> >>>> why most of the time high bit rate signals are analysed for signal=
>
> >>>> integrity issue ??
> >>>>
> >>>> Please explain what is the role of bit rate in signal integrity ??=
>
> >>>>
> >>>> Rajneesh
> >>>>
> >>>>
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> >>>
> >>> --
> >>> Steve Weir
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