Joel,
If you are not looking for very high dynamic range in the measurements,
you can also consider the Teledyne-LeCroy SPARQ unit as an alternative
to multi-channel VNA.
Regards,
Istvan Novak
Oracle
On 5/31/2016 2:27 PM, Joel Brown wrote:
When it is mentioned to incorporate coupons for verification, I assume this
means putting something like an SMA connector at each end to connect a VNA
or TDR. Is there a particular type of SMA and footprint that works best for
this? Should the coupon also include structures in the board design such as
differential vias, component pads as well as microstrip and stripline
traces? It would also be nice to able include connectors between boards to
verify the connector model against measurements. I have looked into the
cost of 20 GHz VNAs and they generally run about $50K or more for a 4 port
and $25K for 2 port. Yuriy mentioned to me that 2 port could be used to
verify measurements and against simulation by using 2 port S-Parameter
results from the simulation or by mathematically calculating the 4 port
S-Parameters from several different 2 port measurements from the VNA.
Obviously the 4 port VNA would be easier and more accurate for differential
S-Parameter measurements. Since we would likely be renting a VNA it might
make make more sense to rent a 4 port model, but if we were buying we could
maybe only afford 2 port.
Thanks - Joel
On Tue, May 31, 2016 at 9:47 AM, SI List <pcb_layup@xxxxxxx> wrote:
Hello:------------------------------------------------------------------
Sharing some data and my experience from the view of PCB maker for
reference.
1. There is a gap between measured and simulated impedance, Especially on
differential stripline. The measured impedance will be bigger than
simulated
impedance 3%~10%<Normal Dk ~Very Low DK> ). So PCB maker need to tweak
trace
width/space. PCB maker will use real cross-section geometry parameters to
back-calculate the DK, and setup a modified material DK database.
2. Back-calculated DK varied from cross-section geometry; single-end or
differential model; prepreg combination etc. We ever did over 500
micro-sections from dedicated standard impedance coupons for Dk
back-calculate analysis. But we confused when we tried to fixed a
back-calculated DK for a material to guide impedance design.
Base Material PP
Style CITS25 SI8000 Datasheet Variation
Isola-FR408 1080
RC63% 3.08 3.12 3.51 0.39
Isola-FR408 2116
RC53% 3.12 3.13 3.73 0.6
Isola-IS415 1080
RC65% 3.05 3.02 3.52 0.5
Isola-IS415 2116
RC55% 3.06 3.08 3.72 0.64
TUC-TU862 1080
RC67% 3.4 3.43 4.1 0.67
TUC-TU862 2116
RC56% 3.63 3.6 4.3 0.7
TUC-TU862 2116
RC60% 3.8 3.81 4.3 0.49
EMC-EM370D 1080
RC63% 3.24 3.28 3.8 0.52
EMC-EM370D 2116
RC52% 3.47 3.44 4.1 0.66
EMC-EM370D 7629
RC44% 3.66 3.7 4.2 0.5
ITEQ-IT200LK 1080
RC65% 3.14 3.15 3.68 0.53
ITEQ-IT200LK 2116
RC57% 3.14 3.13 3.83 0.7
ITEQ-IT200LK 7628
RC50% 3.31 3.3 3.99 0.69
3. Single-end stripline is more sensitive on Z-axis DK, differential
stripline is more sensitive on X-Y axis DK. So Pure resin filled layer and
buttercoat layer will be the key factors to an accurate differential
stripline simulation. But there 2 limitations, A: how to get DK of pure
resin; B: Resin filled differential stripline model seems inaccurate (now
PCB maker used field solver).
4. FR4 glass-resin Mixed dielectric lead to the gap between measured and
simulated impedance. Rotate the layout with 5~15 degree angel will migrate
FWE (I think the impedance wave will more stable), but can not eliminate
the
gap.
5. The back-calculated DK used by PCB maker setup a barrier. Layout cannot
communicate easily with fab house on stackup impedance design. Generic vs.
specific stackups is still a problem. If the DK from datasheet can be used
and useful downstream, the barrier will disappear.
6. DK is not constant, vary from Prepreg combination, copper weight, copper
remain ratio and Z-axis or X-Y axis etc. So the best way to improve
simulation accuracy is the DK simulation technology on a specific stackup.
The key points is get the mixed DK of prepreg combination after lamination
resin flowed and the DK of pure resin. Also accurate filed solver with
resin-filled layer model is necessary.
Reference paper:
Designcon 2013: ACCURATE INSERTION LOSS AND IMPEDANCE MODELING OF PCB
TRACES
Best regards,
Terry Ho
www.sisolver.com
-----邮件原件-----
�件人: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
代表 Jeff Loyer
��时间: 2016年5月31日 22:32
收件人: richard.allred@xxxxxxxxx; Istvan Novak
抄�: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
主题: [SI-LIST] Re: Variation of PCB Dielectric Properties
Hi Richard,
When I was with Intel I was heavily involved in this topic and I believe
our
鈥淔iber Weave Effect: Practical Impact Analysis and Mitigation
Strategies鈥?paper contains a synopsis of the data available. In it we
analyzed the raw data from the work done by the Intel DDR folks to try to
glean the type of statistical data you鈥檙e after 鈥?the net effect of the
fiberglass weave on propagation delay. I鈥�e attached a snapshot from
that
paper (sorry, others won鈥檛 be able to see it) showing the distribution of
the raw data. Bert Simonovich did some work to prove that it can be
replicated in simulation, see http://lamsimenterprises.com/.
To my knowledge, no one has performed further studies 鈥?it was a unique,
wonderful intersection of energies and funds that allowed this study to be
done since it involved so many different material and PCB vendors across
the
world.
Jeff Loyer
Signal and Power Integrity Product Manager
Altium US, www.altium.com
4225 Executive Square, Suite 700
La Jolla, CA 92037
360-819-2520 (cell)
858-864-1580 (desk)
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Richard Allred
Sent: Tuesday, May 31, 2016 5:45 AM
To: Istvan Novak
Cc: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Variation of PCB Dielectric Properties
Thanks for the comments, they helped me clarify my thoughts.
As you guessed, I am interested in finding the statistical distribution of
the dielectric "constant" property across high volume manufacturing so I
can
understand how the absolute delay of the line varies. Determining the
output statistical variation of a system, given the input variable
distribution, is one of my current pet projects.
I was able to find a very interesting presentation by Gary Brist of Intel
(from the early 2000's) where he discusses in extreme detail the
manufacturing process variation for FR4. Slide # 91, 97 and 106 contained
the e_r information was was after.
https://www.jlab.org/eng/eecad/pdf/053designop.pdf
The bottom line is that e_r varies due to the resin content and the spatial
proximity of the copper trace to the glass bundle (weave effect). My guess
is that if there is an updated study on current materials for high speed
PCB
that it is likely proprietary.
Regards,
Richard Allred
On Tue, May 31, 2016 at 6:02 AM, Istvan Novak <istvan.novak@xxxxxxxxxxx>
wrote:
Vadim,available with nondisclosure agreements.
I agree with what you say. In this particular case though the
question came from someone working for an EDA company, making it much
less likely that they can affor or want to go into the business of
designing/evaluating printed circuit boards themselves. Until we get
to a point that the glass and resin electrical properties differ much
less and they are described in more detail on the data sheet, this
question will remain just partially answered. Though to the credit of
laminate and pcb vendors, they have come a long way to supply more
data. A lot is already posted available for everyone and even more is
Regards,wrote:
Istvan Novak
Oracle
On 5/31/2016 3:46 AM, heyfitch (Redacted sender heyfitch for DMARC)
thickness"Hi Richard -
I may not exactly be answering your question here.....
The more you specify to a fab house the less you leave to chance.
You can pick a specific dielectric from a menu of offerings with a
known thickness and a RC (resin content). The so called "pressed out
the target Z.would depend on the % of copper fill. The default number is usually
given for 50%, but you can ask a fab for the number for your design
before you give'em a go. The trace width is what a fab adjusts to hit
(RTF, VLP, HVLP).They don't tweak RC for this purpose. Higher RC dielectric usually
has lower Dk and higher Df. Some dielectric vendors show explicitly
in their datasheets the Dk values for each available option of RC.
The effective Df is very strongly affected by the choice of copper
foil
error.That is if you roll the loss due to copper surface roughness into the
dielectric's Df parameter. It's not necessary to do so if you have
built enough many coupons to unambiguously separate Df and copper
surface roughness parameters in you simulation model (by way
of deembeding generalized model s-parameters.)
This is all good but here comes a reality check...
I have seen internal data from a reputable fab of their own impedance
coupon measurement. To my surprise, the impedance values were
distributed almost uniformly between -10% and +10% of the target.
They did not show any outliers, which made me think the fab used this
coupon measurement - one per panel - for sorting.
With such a uniform distribution their yield must have been quite low.
(For microstrips, the actual Z is also affected by the amount of
over-plating and the solder mask, changing it by up to 3-4 Ohms.).
To muddy up this already confusing picture, one should consider how
fabs use Polar Instrument HW and SW - the de-facto standard with them
- to determine impedance of a panel coupon, which leads to a
systematic
this fab is.But that is a whole other can of worms that I will not get into here.
My recommendation, if you asked for one, is to include you own
connectorized coupons in your design, and measure them; then fit
GMS-parameters with the model. And, yes, "waste" space on the panel
for the coupons; this will make you many friends among project
managers left and right. ;). But, in the end, you will know exactly
the impedance, the dielectric, and surface roughness model
parameters. If you stay with the same fab thru many designs - and
avoid fab brokers - you may even collect useful data on how
consistent
Best regards,
Vadim Heyfitch
Sent from my phone
On May 29, 2016, at 6:03, Richard Allred <richard.allred@xxxxxxxxx>
wrote:
Greetings,
I am aware that typical PCB manufacturers usually guarantee some
impedance target (+/- 10 or 15%) for high speed traces and that they
may use any number of manufacturing controls to achieve this. The
result is that the only way to know the geometric dimensions of a
given sample is to cross-section it.
What I am interested in is, what kind of variation can be expected in
the effective dielectric properties due to the PCB manufacturers
tweaking of the glass/resin ratio and the geometrical variation? Is
anyone aware of a published study that reports this?
Kind regards,
Richard Allred
www.SiSoft.com
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