Yuriy,
How do you factor in phase delay due to copper roughness? Most field solvers
do not have this capability either. It has been shown in various papers that
roughness adds additional phase delay. If roughness is not accounted for,
then that too can account for variation in Dk between manufacturers' data
and measured results.
Bert Simonovich
Signal/Power Integrity Practitioner | Backplane Specialist | Founder
LAMSIM Enterprises Inc.
Web Site: http://lamsimenterprises.com
Blog: http://blog.lamsimenterprises.com/
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Yuriy Shlepnev
Sent: 1-Jun-16 1:25 PM
To: 'Jeff Loyer'
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: ??: Re: Variation of PCB Dielectric Properties
Jeff,
As I mentioned, it is all about the homogenization scale, comparing to the
cross-section.
One dielectric model can be used for loosely coupled traces for instance
with small difference in the velocity or delay of odd and even mode (no
FEXT).
On the other hand, when you see larger difference in the propagation
velocity or delay of two modes (larger FEXT), two-dielectric model is
needed.
Correlating just differential impedance and insertion loss does not provide
a complete solution if you want to use such model in a link path analysis.
See more details and practical examples of model building at our DesignCon
"Lessons learned..." paper #2014_01 at http://www.simberian.com/AppNotes.php
Slides 19 and 22,23 in particular illustrate the need of two-dielectric
model - the FEXT level or modal phase delay can be used to make such
decision.
Best regards,
Yuriy
Yuriy Shlepnev, Ph.D.
President, Simberian Inc.
2629 Townsgate Rd., Suite #235, Westlake Village, CA 91361, USA Office
+1-702-876-2882; Fax +1-702-482-7903 Cell +1-206-409-2368; Virtual
+1-408-627-7706
Skype: shlepnev
www.simberian.com
Simbeor �C Accurate, Productive and Cost-Effective Electromagnetic Signal
Integrity Software 2010 and 2011 DesignVision Award Winner, 2015 Best In
Design&Test Finalist
-----Original Message-----
From: Jeff Loyer [mailto:jeff.loyer@xxxxxxxxxx] ;
Sent: Wednesday, June 1, 2016 10:04 AM
To: shlepnev@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] ??: Re: Variation of PCB Dielectric Properties
Hello Yuriy,
Could you clarify when you need to include the resin layer? In the work
I've seen, it hasn't been necessary to include the resin layer to correlate
differential impedance or insertion loss results, but can affect FEXT
significantly (see DesignCon 2015 paper " PCB Material and Copper Foil
Considerations for Insertion Loss"). Is there a particular frequency or
modeling instance where neglecting the resin layer causes large modeling
errors (compared to measurements).
I.E., when do I need to add the complexity of properly modeling the resin
layer in my simulations, and when can it be neglected?
Thanks,
Jeff Loyer
-----Original Message-----
From: Yuriy Shlepnev [mailto:shlepnev@xxxxxxxxxxxxx]
Sent: Wednesday, June 1, 2016 9:55 AM
To: pcb_layup@xxxxxxx; jeff.loyer@xxxxxxxxxx; richard.allred@xxxxxxxxx;
'Istvan Novak'
Cc: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] ??: Re: Variation of PCB Dielectric Properties
Terry,
Good points, especially #6 - " accurate filed solver with resin-filled layer
model is necessary " :-)
There are 3 key elements in the broadband material model identification with
t-lines (identification with GMS-parameters or with IPC's SPP
technique):
1) High quality measurements;
2) Use of actual geometry of the t-line cross-section;
3) Accurate field solver with proper material and dielectric inhomogeneity
modeling; This is assuming that the test fixtures are properly designed and
manufactured (something like in SPP standard or on Wild River Technology
validation platforms).
Missing one of those key elements will give you the Dk or Df numbers that
are substantially off from the dielectric manufacturer's data. The big
discrepancy, as you observed below, should be actually the first sign that
something is wrong with the procedure or you are dealing with the structures
that requires homogenization approach other than used by the laminate
manufacturer.
As Scott mentioned, the spreadsheet data are usually not so bad. Some
manufacturers, Isola for instance, have accurate Dk values measured for the
Z-direction (wide strip line resonator or Berezkin's method). In the
projects with the Isola's materials we usually end up with just 2-3%
adjustment of Dk for single-ended strips or microstrips (slightly larger Dk
due to presence of the X and Y-components of the electric field in narrower
lines). Same is valid for Meg6 and some other materials from manufacturers
with the established characterization process. The smaller the X and Y
components of the electric field of a line, the closer you should get to the
spreadsheet values of Dk at the specified frequency. It is all about the
homogenization and scale - see more at our DesignCon tutorial -#2016_01 at
http://www.simberian.com/TechnicalPresentations.php
Following the homogenization scale approach, we can conclude that the
inhomogeneous dielectric cannot be uniquely homogenized for the cases of
tightly coupled strip or microstrip differential lines. To have correlation
in the impedance and propagation constant for both differential and common
modes you will need a model with at least two dielectrics - resin or solder
mask and the homogenized mixture. When model for resin is not available
(those are proprietary mixtures :-), you can derive it from the glass model
(you can get this data from the fabric
manufacturers) and volumetric resin content as it is done in our paper
#2014_04 at http://www.simberian.com/AppNotes.php.
Best regards,
Yuriy
Yuriy Shlepnev, Ph.D.
President, Simberian Inc.
2629 Townsgate Rd., Suite #235, Westlake Village, CA 91361, USA Office
+1-702-876-2882; Fax +1-702-482-7903 Cell +1-206-409-2368; Virtual
+1-408-627-7706
Skype: shlepnev
www.simberian.com
Simbeor C Accurate, Productive and Cost-Effective Electromagnetic Signal
Integrity Software
2010 and 2011 DesignVision Award Winner, 2015 Best In Design&Test Finalist
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of SI List
Sent: Tuesday, May 31, 2016 9:47 AM
To: jeff.loyer@xxxxxxxxxx; richard.allred@xxxxxxxxx; 'Istvan Novak'
Cc: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] ??: Re: Variation of PCB Dielectric Properties
Hello:
Sharing some data and my experience from the view of PCB maker for
reference.
1. There is a gap between measured and simulated impedance, Especially on
differential stripline. The measured impedance will be bigger than simulated
impedance 3%~10%<Normal Dk ~Very Low DK> ). So PCB maker need to tweak trace
width/space. PCB maker will use real cross-section geometry parameters to
back-calculate the DK, and setup a modified material DK database.
2. Back-calculated DK varied from cross-section geometry; single-end or
differential model; prepreg combination etc. We ever did over 500
micro-sections from dedicated standard impedance coupons for Dk
back-calculate analysis. But we confused when we tried to fixed a
back-calculated DK for a material to guide impedance design.
Base Material PP
Style CITS25 SI8000 Datasheet Variation
Isola-FR408 1080
RC63% 3.08 3.12 3.51 0.39
Isola-FR408 2116
RC53% 3.12 3.13 3.73 0.6
Isola-IS415 1080
RC65% 3.05 3.02 3.52 0.5
Isola-IS415 2116
RC55% 3.06 3.08 3.72 0.64
TUC-TU862 1080
RC67% 3.4 3.43 4.1 0.67
TUC-TU862 2116
RC56% 3.63 3.6 4.3 0.7
TUC-TU862 2116
RC60% 3.8 3.81 4.3 0.49
EMC-EM370D 1080
RC63% 3.24 3.28 3.8 0.52
EMC-EM370D 2116
RC52% 3.47 3.44 4.1 0.66
EMC-EM370D 7629
RC44% 3.66 3.7 4.2 0.5
ITEQ-IT200LK 1080
RC65% 3.14 3.15 3.68 0.53
ITEQ-IT200LK 2116
RC57% 3.14 3.13 3.83 0.7
ITEQ-IT200LK 7628
RC50% 3.31 3.3 3.99 0.69
3. Single-end stripline is more sensitive on Z-axis DK, differential
stripline is more sensitive on X-Y axis DK. So Pure resin filled layer and
buttercoat layer will be the key factors to an accurate differential
stripline simulation. But there 2 limitations, A: how to get DK of pure
resin; B: Resin filled differential stripline model seems inaccurate (now
PCB maker used field solver).
4. FR4 glass-resin Mixed dielectric lead to the gap between measured and
simulated impedance. Rotate the layout with 5~15 degree angel will migrate
FWE (I think the impedance wave will more stable), but can not eliminate the
gap.
5. The back-calculated DK used by PCB maker setup a barrier. Layout cannot
communicate easily with fab house on stackup impedance design. Generic vs.
specific stackups is still a problem. If the DK from datasheet can be used
and useful downstream, the barrier will disappear.
6. DK is not constant, vary from Prepreg combination, copper weight, copper
remain ratio and Z-axis or X-Y axis etc. So the best way to improve
simulation accuracy is the DK simulation technology on a specific stackup.
The key points is get the mixed DK of prepreg combination after lamination
resin flowed and the DK of pure resin. Also accurate filed solver with
resin-filled layer model is necessary.
Reference paper:
Designcon 2013: ACCURATE INSERTION LOSS AND IMPEDANCE MODELING OF PCB TRACES
Best regards,
Terry Ho
www.sisolver.com
-----邮件原件-----
发件人: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
代表 Jeff Loyer
发送时间: 2016年5月31日 22:32
收件人: richard.allred@xxxxxxxxx; Istvan Novak
抄送: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
主题: [SI-LIST] Re: Variation of PCB Dielectric Properties
Hi Richard,
When I was with Intel I was heavily involved in this topic and I believe our
Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies
?paper contains a synopsis of the data available. In it we analyzed the raw
data from the work done by the Intel DDR folks to try to glean the type of
statistical data you re after ?the net effect of the fiberglass weave on
propagation delay. I ve attached a snapshot from that paper (sorry, others
won t be able to see it) showing the distribution of the raw data. Bert
Simonovich did some work to prove that it can be replicated in simulation,
see http://lamsimenterprises.com/.
To my knowledge, no one has performed further studies ?it was a unique,
wonderful intersection of energies and funds that allowed this study to be
done since it involved so many different material and PCB vendors across the
world.
Jeff Loyer
Signal and Power Integrity Product Manager
Altium US, www.altium.com
4225 Executive Square, Suite 700
La Jolla, CA 92037
360-819-2520 (cell)
858-864-1580 (desk)
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Richard Allred
Sent: Tuesday, May 31, 2016 5:45 AM
To: Istvan Novak
Cc: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Variation of PCB Dielectric Properties
Thanks for the comments, they helped me clarify my thoughts.
As you guessed, I am interested in finding the statistical distribution of
the dielectric "constant" property across high volume manufacturing so I can
understand how the absolute delay of the line varies. Determining the
output statistical variation of a system, given the input variable
distribution, is one of my current pet projects.
I was able to find a very interesting presentation by Gary Brist of Intel
(from the early 2000's) where he discusses in extreme detail the
manufacturing process variation for FR4. Slide # 91, 97 and 106 contained
the e_r information was was after.
https://www.jlab.org/eng/eecad/pdf/053designop.pdf
The bottom line is that e_r varies due to the resin content and the spatial
proximity of the copper trace to the glass bundle (weave effect). My guess
is that if there is an updated study on current materials for high speed PCB
that it is likely proprietary.
Regards,
Richard Allred
On Tue, May 31, 2016 at 6:02 AM, Istvan Novak <istvan.novak@xxxxxxxxxxx>
wrote:
Vadim,
I agree with what you say. In this particular case though the
question came from someone working for an EDA company, making it much
less likely that they can affor or want to go into the business of
designing/evaluating printed circuit boards themselves. Until we get
to a point that the glass and resin electrical properties differ much
less and they are described in more detail on the data sheet, this
question will remain just partially answered. Though to the credit of
laminate and pcb vendors, they have come a long way to supply more
data. A lot is already posted available for everyone and even more isavailable with nondisclosure agreements.
Regards,
Istvan Novak
Oracle
On 5/31/2016 3:46 AM, heyfitch (Redacted sender heyfitch for DMARC)wrote:
Hi Richard -
I may not exactly be answering your question here.....
The more you specify to a fab house the less you leave to chance.
You can pick a specific dielectric from a menu of offerings with a
thickness"known thickness and a RC (resin content). The so called "pressed out
would depend on the % of copper fill. The default number is usually
given for 50%, but you can ask a fab for the number for your design
the target Z.before you give'em a go. The trace width is what a fab adjusts to hit
They don't tweak RC for this purpose. Higher RC dielectric usually
has lower Dk and higher Df. Some dielectric vendors show explicitly
in their datasheets the Dk values for each available option of RC.
(RTF, VLP, HVLP).The effective Df is very strongly affected by the choice of copper
foil
That is if you roll the loss due to copper surface roughness into the
dielectric's Df parameter. It's not necessary to do so if you have
built enough many coupons to unambiguously separate Df and copper
surface roughness parameters in you simulation model (by way
of deembeding generalized model s-parameters.)
This is all good but here comes a reality check...
I have seen internal data from a reputable fab of their own impedance
coupon measurement. To my surprise, the impedance values were
distributed almost uniformly between -10% and +10% of the target.
They did not show any outliers, which made me think the fab used this
coupon measurement - one per panel - for sorting.
With such a uniform distribution their yield must have been quite low.
(For microstrips, the actual Z is also affected by the amount of
over-plating and the solder mask, changing it by up to 3-4 Ohms.).
To muddy up this already confusing picture, one should consider how
fabs use Polar Instrument HW and SW - the de-facto standard with them
error.- to determine impedance of a panel coupon, which leads to a
systematic
But that is a whole other can of worms that I will not get into here.
My recommendation, if you asked for one, is to include you own
connectorized coupons in your design, and measure them; then fit
GMS-parameters with the model. And, yes, "waste" space on the panel
for the coupons; this will make you many friends among project
managers left and right. ;). But, in the end, you will know exactly
the impedance, the dielectric, and surface roughness model
parameters. If you stay with the same fab thru many designs - and
this fab is.avoid fab brokers - you may even collect useful data on how
consistent
Best regards,
Vadim Heyfitch
Sent from my phone
On May 29, 2016, at 6:03, Richard Allred <richard.allred@xxxxxxxxx>
wrote:
Greetings,
I am aware that typical PCB manufacturers usually guarantee some
impedance target (+/- 10 or 15%) for high speed traces and that they
may use any number of manufacturing controls to achieve this. The
result is that the only way to know the geometric dimensions of a
given sample is to cross-section it.
What I am interested in is, what kind of variation can be expected in
the effective dielectric properties due to the PCB manufacturers
tweaking of the glass/resin ratio and the geometrical variation? Is
anyone aware of a published study that reports this?
Kind regards,
Richard Allred
www.SiSoft.com
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