Hi Richard -
I may not exactly be answering your question here.....
The more you specify to a fab house the less you leave to chance. You can
pick a specific dielectric from a menu of offerings with a known thickness and
a RC (resin content). The so called "pressed out thickness" would depend on
the % of copper fill. The default number is usually given for 50%, but you can
ask a fab for the number for your design before you give'em a go. The trace
width is what a fab adjusts to hit the target Z. They don't tweak RC for this
purpose. Higher RC dielectric usually has lower Dk and higher Df. Some
dielectric vendors show explicitly in their datasheets the Dk values for each
available option of RC. The effective Df is very strongly affected by the
choice of copper foil (RTF, VLP, HVLP). That is if you roll the loss due to
copper surface roughness into the dielectric's Df parameter. It's not
necessary to do so if you have built enough many coupons to unambiguously
separate Df and copper surface roughness parameters in you simulation model (by
way of deembeding generalized model s-parameters.)
This is all good but here comes a reality check...
I have seen internal data from a reputable fab of their own impedance coupon
measurement. To my surprise, the impedance values were distributed almost
uniformly between -10% and +10% of the target. They did not show any outliers,
which made me think the fab used this coupon measurement - one per panel - for
sorting.
With such a uniform distribution their yield must have been quite low.
(For microstrips, the actual Z is also affected by the amount of over-plating
and the solder mask, changing it by up to 3-4 Ohms.).
To muddy up this already confusing picture, one should consider how fabs use
Polar Instrument HW and SW - the de-facto standard with them - to determine
impedance of a panel coupon, which leads to a systematic error. But that is a
whole other can of worms that I will not get into here.
My recommendation, if you asked for one, is to include you own connectorized
coupons in your design, and measure them; then fit GMS-parameters with the
model. And, yes, "waste" space on the panel for the coupons; this will make you
many friends among project managers left and right. ;). But, in the end, you
will know exactly the impedance, the dielectric, and surface roughness model
parameters. If you stay with the same fab thru many designs - and avoid fab
brokers - you may even collect useful data on how consistent this fab is.
Best regards,
Vadim Heyfitch
Sent from my phone
On May 29, 2016, at 6:03, Richard Allred <richard.allred@xxxxxxxxx> wrote:
Greetings,
I am aware that typical PCB manufacturers usually guarantee some impedance
target (+/- 10 or 15%) for high speed traces and that they may use any
number of manufacturing controls to achieve this. The result is that the
only way to know the geometric dimensions of a given sample is to
cross-section it.
What I am interested in is, what kind of variation can be expected in the
effective dielectric properties due to the PCB manufacturers tweaking of
the glass/resin ratio and the geometrical variation? Is anyone aware of a
published study that reports this?
Kind regards,
Richard Allred
www.SiSoft.com
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