[SI-LIST] Re: REG AC Capacitive Loading
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sat, 02 Jun 2012 06:42:46 -0700
50pF for a single input sounds like someone cut and pasted a spec from
inside some prehistoric cave painting. Is the buffer made with MSI from
1975? You should seriously question any values above about 8pF.
Steve.
On 5/31/2012 8:59 PM, Vinothkumar D wrote:
> Hello Everyone,
>
> I have a problem in AC loading in which the Cout of FPGA<< Cin of a Bus
> controller. I have used a buffer between FPGA and Bus controller still I
> could not meet ac loading requirements.
> Eg:
> FPGA Cout = 5pF
> Buffer Cin = 5pF and Cout = 50pf
> Each Bus controller Cin = 50pF
> Total Bus controllers Cin = 150pf
>
> Now I have connected the ADD/DATA and control pins through Buffer which is
> driving three bus controllers, I am meeting the ac loading requirements.
>
> Will it create any timing issue . Please help me on this.
>
> Regards
> Vinothkumar.D
> E-mail ID : Vinothkumar.D@xxxxxxxxxx
>
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